193 lines
5.5 KiB
C
193 lines
5.5 KiB
C
/* $NetBSD: sysreg.h,v 1.1 2014/09/19 17:36:26 matt Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RISCV_SYSREG_H_
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#define _RISCV_SYSREG_H_
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#ifndef _KERNEL
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#include <sys/param.h>
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#endif
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#define FCSR_FMASK 0 // no exception bits
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#define FCSR_FRM __BITS(7,5)
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#define FCSR_FRM_RNE 0b000 // Round Nearest, ties to Even
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#define FCSR_FRM_RTZ 0b001 // Round Towards Zero
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#define FCSR_FRM_RDN 0b010 // Round DowN (-infinity)
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#define FCSR_FRM_RUP 0b011 // Round UP (+infinity)
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#define FCSR_FRM_RMM 0b100 // Round to nearest, ties to Max Magnitude
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#define FCSR_FFLAGS __BITS(4,0) // Sticky bits
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#define FCSR_NV __BIT(4) // iNValid operation
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#define FCSR_DZ __BIT(3) // Divide by Zero
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#define FCSR_OF __BIT(2) // OverFlow
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#define FCSR_UF __BIT(1) // UnderFlow
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#define FCSR_NX __BIT(0) // iNeXact
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static inline uint32_t
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riscvreg_fcsr_read(void)
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{
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uint32_t __fcsr;
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__asm("frcsr %0" : "=r"(__fcsr));
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return __fcsr;
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}
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static inline uint32_t
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riscvreg_fcsr_write(uint32_t __new)
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{
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uint32_t __old;
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__asm("fscsr %0, %1" : "=r"(__old) : "r"(__new));
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return __old;
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}
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static inline uint32_t
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riscvreg_fcsr_read_fflags(void)
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{
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uint32_t __old;
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__asm("frflags %0" : "=r"(__old));
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return __SHIFTOUT(__old, FCSR_FFLAGS);
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}
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static inline uint32_t
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riscvreg_fcsr_write_fflags(uint32_t __new)
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{
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uint32_t __old;
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__new = __SHIFTIN(__new, FCSR_FFLAGS);
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__asm("fsflags %0, %1" : "=r"(__old) : "r"(__new));
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return __SHIFTOUT(__old, FCSR_FFLAGS);
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}
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static inline uint32_t
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riscvreg_fcsr_read_frm(void)
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{
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uint32_t __old;
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__asm("frrm\t%0" : "=r"(__old));
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return __SHIFTOUT(__old, FCSR_FRM);
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}
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static inline uint32_t
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riscvreg_fcsr_write_frm(uint32_t __new)
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{
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uint32_t __old;
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__new = __SHIFTIN(__new, FCSR_FRM);
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__asm volatile("fsrm\t%0, %1" : "=r"(__old) : "r"(__new));
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return __SHIFTOUT(__old, FCSR_FRM);
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}
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// Status Register
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#define SR_IP __BITS(31,24) // Pending interrupts
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#define SR_IM __BITS(23,16) // Interrupt Mask
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#define SR_VM __BIT(7) // MMU On
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#define SR_S64 __BIT(6) // RV64 supervisor mode
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#define SR_U64 __BIT(5) // RV64 user mode
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#define SR_EF __BIT(4) // Enable Floating Point
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#define SR_PEI __BIT(3) // Previous EI setting
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#define SR_EI __BIT(2) // Enable interrupts
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#define SR_PS __BIT(1) // Previous (S) supervisor setting
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#define SR_S __BIT(0) // Supervisor
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#ifdef _LP64
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#define SR_USER (SR_EI|SR_U64|SR_S64|SR_VM|SR_IM)
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#define SR_USER32 (SR_USER & ~SR_U64)
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#define SR_KERNEL (SR_S|SR_EI|SR_U64|SR_S64|SR_VM)
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#else
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#define SR_USER (SR_EI|SR_VM|SR_IM)
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#define SR_KERNEL (SR_S|SR_EI|SR_VM)
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#endif
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static inline uint32_t
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riscvreg_status_read(void)
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{
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uint32_t __sr;
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__asm("csrr\t%0, status" : "=r"(__sr));
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return __sr;
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}
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static inline uint32_t
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riscvreg_status_clear(uint32_t __mask)
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{
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uint32_t __sr;
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if (__builtin_constant_p(__mask) && __mask < 0x20) {
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__asm("csrrci\t%0, status, %1" : "=r"(__sr) : "i"(__mask));
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} else {
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__asm("csrrc\t%0, status, %1" : "=r"(__sr) : "r"(__mask));
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}
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return __sr;
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}
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static inline uint32_t
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riscvreg_status_set(uint32_t __mask)
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{
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uint32_t __sr;
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if (__builtin_constant_p(__mask) && __mask < 0x20) {
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__asm("csrrsi\t%0, status, %1" : "=r"(__sr) : "i"(__mask));
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} else {
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__asm("csrrs\t%0, status, %1" : "=r"(__sr) : "r"(__mask));
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}
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return __sr;
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}
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// Cause register
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#define CAUSE_MISALIGNED_FETCH 0
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#define CAUSE_FAULT_FETCH 1
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#define CAUSE_ILLEGAL_INSTRUCTION 2
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#define CAUSE_PRIVILEGED_INSTRUCTION 3
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#define CAUSE_FP_DISABLED 4
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#define CAUSE_SYSCALL 6
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#define CAUSE_BREAKPOINT 7
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#define CAUSE_MISALIGNED_LOAD 8
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#define CAUSE_MISALIGNED_STORE 9
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#define CAUSE_FAULT_LOAD 10
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#define CAUSE_FAULT_STORE 11
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#define CAUSE_ACCELERATOR_DISABLED 12
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static inline uint64_t
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riscvreg_cycle_read(void)
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{
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#ifdef _LP64
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uint64_t __lo;
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__asm __volatile("csrr\t%0,cycle" : "=r"(__lo));
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return __lo;
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#else
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uint32_t __hi0, __hi1, __lo0;
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do {
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__asm __volatile(
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"csrr\t%[__hi0], cycleh"
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"\n\t" "csrr\t%[__lo0], cycle"
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"\n\t" "csrr\t%[__hi1], cycleh"
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: [__hi0] "=r"(__hi0),
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[__lo0] "=r"(__lo0),
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[__hi1] "=r"(__hi1));
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} while (__hi0 != __hi1);
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return ((uint64_t)__hi0 << 32) | (uint64_t)__lo0;
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#endif
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}
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#endif /* _RISCV_SYSREG_H_ */
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