357 lines
8.9 KiB
C
357 lines
8.9 KiB
C
/* $NetBSD: dic.c,v 1.3 2011/07/28 02:07:42 uebayasi Exp $ */
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/*
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* Copyright (c) 2010, 2011 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: dic.c,v 1.3 2011/07/28 02:07:42 uebayasi Exp $");
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#define _INTR_PRIVATE /* for arm/pic/picvar.h */
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#include "locators.h"
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#include "opt_dic.h"
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#include <sys/param.h>
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#include <sys/evcnt.h>
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#include <sys/device.h>
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#include <sys/atomic.h>
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#include <machine/intr.h>
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#include <sys/bus.h>
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#include <uvm/uvm_extern.h>
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#include <arm/cpu.h>
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#include <arm/armreg.h>
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#include <arm/cpufunc.h>
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#include <arm/pic/picvar.h>
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#include <arm/mpcore/mpcorevar.h>
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#include <arm/mpcore/mpcorereg.h>
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#include <arm/mpcore/dicreg.h>
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#include <machine/autoconf.h>
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/*
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* 0 is the highest priority.
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*/
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#define HW_TO_SW_IPL(ipl) (IPL_HIGH - (ipl))
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#define SW_TO_HW_IPL(ipl) (IPL_HIGH - (ipl))
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struct dic_softc {
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device_t sc_dev;
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struct pic_softc sc_pic;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_cii_ioh;
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volatile uint32_t *sc_cii_vaddr; /* CPU interface */
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bus_space_handle_t sc_gid_ioh;
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volatile uint32_t *sc_gid_vaddr; /* Global distributor */
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int sc_nsrcs;
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// uint32_t sc_enabled_mask[4];
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};
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#define PIC_TO_SOFTC(pic) \
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((struct dic_softc *)((char *)(pic) - \
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offsetof(struct dic_softc, sc_pic)))
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static int dic_match(device_t, cfdata_t, void *);
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static void dic_attach(device_t, device_t, void *);
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static void dic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
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static void dic_block_irqs(struct pic_softc *, size_t, uint32_t);
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static void dic_establish_irq(struct pic_softc *, struct intrsource *);
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#define DIC_READ(sc, offset) \
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(*((sc)->sc_gid_vaddr + (offset) / sizeof (uint32_t)))
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#define DIC_WRITE(sc, offset, val) \
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(*((sc)->sc_gid_vaddr + (offset) / sizeof (uint32_t)) = (val))
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#define CII_READ(sc, offset) \
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(*((sc)->sc_cii_vaddr + (offset) / sizeof (uint32_t)))
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#define CII_WRITE(sc, offset, val) \
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(*((sc)->sc_cii_vaddr + (offset) / sizeof (uint32_t)) = (val))
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const struct pic_ops dic_pic_ops = {
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.pic_unblock_irqs = dic_unblock_irqs,
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.pic_block_irqs = dic_block_irqs,
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.pic_establish_irq = dic_establish_irq,
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.pic_source_name = NULL
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};
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CFATTACH_DECL_NEW(dic, sizeof(struct dic_softc),
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dic_match, dic_attach, NULL, NULL);
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struct dic_softc *dic_softc;
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static int
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dic_match(device_t parent, cfdata_t cf, void *aux)
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{
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if (strcmp(cf->cf_name, "dic") == 0)
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return 1;
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return 0;
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}
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static void
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dic_attach(device_t parent, device_t self, void *aux)
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{
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struct dic_softc *dic = device_private(self);
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struct pmr_attach_args * const pa = aux;
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uint32_t typ;
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aprint_normal(": Distributed Interrupt Controller\n");
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aprint_naive("\n");
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dic->sc_dev = self;
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dic->sc_iot = pa->pa_iot;
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dic_softc = dic;
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if (bus_space_subregion(dic->sc_iot, pa->pa_ioh,
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MPCORE_PMR_CII, MPCORE_PMR_CII_SIZE,
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&dic->sc_cii_ioh) ||
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bus_space_subregion(dic->sc_iot, pa->pa_ioh,
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MPCORE_PMR_GID, MPCORE_PMR_GID_SIZE,
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&dic->sc_gid_ioh)) {
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aprint_error_dev(self, "can't subregion\n");
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return;
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}
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dic->sc_cii_vaddr = bus_space_vaddr(dic->sc_iot, dic->sc_cii_ioh);
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dic->sc_gid_vaddr = bus_space_vaddr(dic->sc_iot, dic->sc_gid_ioh);
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typ = DIC_READ(dic, DIC_TYPE);
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dic->sc_nsrcs =
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32 * (1 +
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((typ & DIC_TYPE_NLINES_MASK) >> DIC_TYPE_NLINES_SHIFT));
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aprint_normal_dev(self, "%d CPUs, %d interrupt sources\n",
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1 + (u_int)((typ & DIC_TYPE_NCPUS_MASK) >> DIC_TYPE_NCPUS_SHIFT),
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dic->sc_nsrcs);
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DIC_WRITE(dic, DIC_CONTROL, DIC_CONTROL_ENABLE);
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CII_WRITE(dic, CII_CONTROL, CII_CONTROL_ENABLE);
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dic->sc_pic.pic_ops = &dic_pic_ops;
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dic->sc_pic.pic_maxsources = dic->sc_nsrcs;
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strlcpy(dic->sc_pic.pic_name, device_xname(self),
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sizeof(dic->sc_pic.pic_name));
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pic_add(&dic->sc_pic, 0);
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enable_interrupts(I32_bit|F32_bit);
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}
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void
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dic_unblock_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
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{
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struct dic_softc * const dic = PIC_TO_SOFTC(pic);
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size_t group = irq_base / 32;
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DIC_WRITE(dic, DIC_ENSET(group), irq_mask);
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}
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void
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dic_block_irqs(struct pic_softc *pic, size_t irq_base, uint32_t irq_mask)
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{
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struct dic_softc * const dic = PIC_TO_SOFTC(pic);
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size_t group = irq_base / 32;
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DIC_WRITE(dic, DIC_ENCLEAR(group), irq_mask);
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}
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static __inline u_int
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my_core_id(void)
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{
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uint32_t id;
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__asm ("mrc p15, 0, %0, c0, c0, 5" : "=r" (id));
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return id & 0x0f;
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}
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static void
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dic_establish_irq(struct pic_softc *pic, struct intrsource *is)
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{
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struct dic_softc * const dic = PIC_TO_SOFTC(pic);
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int irq = is->is_irq;
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int shift;
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int group;
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uint32_t reg;
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KASSERT(irq < dic->sc_nsrcs);
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KASSERT(is->is_ipl < 16);
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#ifdef NO_DIC_INITIALIZE
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/*
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* DIC is configured by the firmware.
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* don't change the settings.
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*/
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#else
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group = irq / 4;
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shift = (irq % 4) * 8 + 4;
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reg = DIC_READ(dic, DIC_PRIORITY(group));
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reg &= ~(0xf << shift);
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reg |= SW_TO_HW_IPL(is->is_ipl) << shift;
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DIC_WRITE(dic, DIC_PRIORITY(group), reg);
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/* edge or level triggered.
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* always use 1-N interrupt software model.
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* XXX: limited to high-level or rising-edege trigger.
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*/
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shift = (irq % 16) * 2;
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group = (irq / 16);
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reg = DIC_READ(dic, DIC_CONFIG(group));
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reg &= ~(0x03 << shift);
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if (is->is_type == IST_EDGE)
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reg |= 0x01 << shift;
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else
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reg |= 0x03 << shift;
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DIC_WRITE(dic, DIC_CONFIG(group), reg);
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group = irq / 4;
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shift = (irq % 4) * 8;
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reg = DIC_READ(dic, DIC_TARGET(group));
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reg &= ~(0x0f << shift);
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#ifdef MULTIPROCESSOR
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#error not yet.
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#else
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reg |= 1 << (my_core_id() + shift);
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#endif
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DIC_WRITE(dic, DIC_TARGET(group), reg);
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#endif /* NO_DIC_INITIALIZE */
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/* enable the interrupt */
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group = irq / 32;
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DIC_WRITE(dic, DIC_ENSET(group), 1 << (irq % 32));
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}
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void
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mpcore_irq_handler(void *frame)
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{
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struct cpu_info * const ci = curcpu();
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int irq;
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uint32_t reg, intack;
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ci->ci_data.cpu_nintr++;
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for (;;) {
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struct intrsource *is;
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intack = CII_READ(dic_softc, CII_INTACK);
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irq = intack & CII_INTACK_INTID_MASK;
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if (irq == 1023) /* spurious */
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break;
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reg = CII_READ(dic_softc, CII_RUNPRI);
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CII_WRITE(dic_softc, CII_PRIMASK, reg);
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is = dic_softc->sc_pic.pic_sources[irq];
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if (__predict_true(is != NULL)) {
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int oldipl = ci->ci_cpl;
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ci->ci_cpl = HW_TO_SW_IPL((reg & CII_PRIMASK_MASK)
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>> CII_PRIMASK_SHIFT);
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cpsie(I32_bit);
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pic_dispatch(is, frame);
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cpsid(I32_bit);
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ci->ci_cpl = oldipl;
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CII_WRITE(dic_softc, CII_PRIMASK,
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SW_TO_HW_IPL(oldipl) << CII_PRIMASK_SHIFT);
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}
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CII_WRITE(dic_softc, CII_EOI, intack);
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}
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#ifdef DIC_CASCADED_IRQ
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/* handle cascaded interrupts through PIC framework */
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pic_do_pending_ints(I32_bit, ci->ci_cpl, frame);
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#endif
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}
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int
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_splraise(int newipl)
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{
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struct cpu_info * const ci = curcpu();
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const int oldipl = ci->ci_cpl;
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KASSERT(newipl < NIPL);
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if (newipl > ci->ci_cpl) {
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register_t psw = disable_interrupts(I32_bit);
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ci->ci_cpl = newipl;
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CII_WRITE(dic_softc, CII_PRIMASK,
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SW_TO_HW_IPL(newipl) << CII_PRIMASK_SHIFT);
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restore_interrupts(psw);
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}
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return oldipl;
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}
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int
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_spllower(int newipl)
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{
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struct cpu_info * const ci = curcpu();
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const int oldipl = ci->ci_cpl;
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KASSERT(panicstr || newipl <= ci->ci_cpl);
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if (newipl < ci->ci_cpl) {
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register_t psw = disable_interrupts(I32_bit);
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CII_WRITE(dic_softc, CII_PRIMASK,
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SW_TO_HW_IPL(newipl) << CII_PRIMASK_SHIFT);
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pic_do_pending_ints(psw, newipl, NULL);
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restore_interrupts(psw);
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}
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return oldipl;
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}
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void
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splx(int savedipl)
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{
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struct cpu_info * const ci = curcpu();
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KASSERT(savedipl < NIPL);
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if (savedipl < ci->ci_cpl) {
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register_t psw = disable_interrupts(I32_bit);
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CII_WRITE(dic_softc, CII_PRIMASK,
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SW_TO_HW_IPL(savedipl) << CII_PRIMASK_SHIFT);
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#ifdef DIC_CASCADED_IRQ
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pic_do_pending_ints(psw, savedipl, NULL);
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#endif
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restore_interrupts(psw);
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}
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ci->ci_cpl = savedipl;
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}
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