420 lines
10 KiB
C
420 lines
10 KiB
C
/* $NetBSD: imxspi.c,v 1.2 2014/03/29 12:00:27 hkenken Exp $ */
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/*-
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* Copyright (c) 2014 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* this module support CSPI and eCSPI.
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* i.MX51 have 2 eCSPI and 1 CSPI modules.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imxspi.c,v 1.2 2014/03/29 12:00:27 hkenken Exp $");
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#include "opt_imx.h"
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#include "opt_imxspi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/proc.h>
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#include <sys/intr.h>
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#include <sys/bus.h>
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#include <machine/cpu.h>
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#include <machine/intr.h>
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#include <arm/imx/imxspivar.h>
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#include <arm/imx/imxspireg.h>
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/* SPI service routines */
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static int imxspi_configure_enhanced(void *, int, int, int);
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static int imxspi_configure(void *, int, int, int);
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static int imxspi_transfer(void *, struct spi_transfer *);
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static int imxspi_intr(void *);
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/* internal stuff */
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void imxspi_done(struct imxspi_softc *, int);
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void imxspi_send(struct imxspi_softc *);
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void imxspi_recv(struct imxspi_softc *);
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void imxspi_sched(struct imxspi_softc *);
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#define IMXSPI(x) \
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((sc->sc_enhanced) ? __CONCAT(ECSPI_, x) : __CONCAT(CSPI_, x))
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#define READ_REG(sc, x) \
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x))
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#define WRITE_REG(sc, x, v) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXSPI(x), (v))
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#ifdef IMXSPI_DEBUG
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int imxspi_debug = IMXSPI_DEBUG;
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#define DPRINTFN(n,x) if (imxspi_debug>(n)) printf x;
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#else
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#define DPRINTFN(n,x)
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#endif
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int
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imxspi_attach_common(device_t parent, struct imxspi_softc *sc, void *aux)
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{
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struct imxspi_attach_args *saa = aux;
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struct spibus_attach_args sba;
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bus_addr_t addr = saa->saa_addr;
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bus_size_t size = saa->saa_size;
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sc->sc_iot = saa->saa_iot;
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sc->sc_freq = saa->saa_freq;
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sc->sc_tag = saa->saa_tag;
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sc->sc_enhanced = saa->saa_enhanced;
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if (size <= 0)
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size = SPI_SIZE;
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if (bus_space_map(sc->sc_iot, addr, size, 0, &sc->sc_ioh)) {
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aprint_error_dev(sc->sc_dev, "couldn't map registers\n");
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return 1;
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}
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aprint_normal(": i.MX %sCSPI Controller (clock %ld Hz)\n",
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((sc->sc_enhanced) ? "e" : ""), sc->sc_freq);
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/* Initialize SPI controller */
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sc->sc_spi.sct_cookie = sc;
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if (sc->sc_enhanced)
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sc->sc_spi.sct_configure = imxspi_configure_enhanced;
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else
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sc->sc_spi.sct_configure = imxspi_configure;
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sc->sc_spi.sct_transfer = imxspi_transfer;
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/* sc->sc_spi.sct_nslaves must have been initialized by machdep code */
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sc->sc_spi.sct_nslaves = saa->saa_nslaves;
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if (!sc->sc_spi.sct_nslaves)
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aprint_error_dev(sc->sc_dev, "no slaves!\n");
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sba.sba_controller = &sc->sc_spi;
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/* initialize the queue */
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SIMPLEQ_INIT(&sc->sc_q);
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/* configure SPI */
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/* Setup Control Register */
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WRITE_REG(sc, CONREG, __SHIFTIN(0, IMXSPI(CON_DRCTL)) |
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__SHIFTIN(8 - 1, IMXSPI(CON_BITCOUNT)) |
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__SHIFTIN(0xf, IMXSPI(CON_MODE)) | IMXSPI(CON_ENABLE));
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/* TC and RR interruption */
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WRITE_REG(sc, INTREG, (IMXSPI(INTR_TC_EN) | IMXSPI(INTR_RR_EN)));
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WRITE_REG(sc, STATREG, IMXSPI(STAT_CLR));
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WRITE_REG(sc, PERIODREG, 0x0);
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/* enable device interrupts */
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sc->sc_ih = intr_establish(saa->saa_irq, IPL_BIO, IST_LEVEL,
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imxspi_intr, sc);
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/* attach slave devices */
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(void)config_found_ia(sc->sc_dev, "spibus", &sba, spibus_print);
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return 0;
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}
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static int
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imxspi_configure(void *arg, int slave, int mode, int speed)
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{
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struct imxspi_softc *sc = arg;
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uint32_t div_cnt = 0;
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uint32_t div;
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uint32_t contrl = 0;
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div = (sc->sc_freq + (speed - 1)) / speed;
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div = div - 1;
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for (div_cnt = 0; div > 0; div_cnt++)
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div >>= 1;
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div_cnt = div_cnt - 2;
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if (div_cnt >= 7)
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div_cnt = 7;
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contrl = READ_REG(sc, CONREG);
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contrl &= ~CSPI_CON_DIV;
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contrl |= __SHIFTIN(div_cnt, CSPI_CON_DIV);
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contrl &= ~(CSPI_CON_POL | CSPI_CON_PHA);
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switch (mode) {
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case SPI_MODE_0:
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/* CPHA = 0, CPOL = 0 */
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break;
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case SPI_MODE_1:
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/* CPHA = 1, CPOL = 0 */
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contrl |= CSPI_CON_PHA;
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break;
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case SPI_MODE_2:
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/* CPHA = 0, CPOL = 1 */
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contrl |= CSPI_CON_POL;
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break;
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case SPI_MODE_3:
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/* CPHA = 1, CPOL = 1 */
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contrl |= CSPI_CON_POL;
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contrl |= CSPI_CON_PHA;
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break;
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default:
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return EINVAL;
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}
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WRITE_REG(sc, CONREG, contrl);
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DPRINTFN(3, ("%s: slave %d mode %d speed %d\n",
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__func__, slave, mode, speed));
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return 0;
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}
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static int
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imxspi_configure_enhanced(void *arg, int slave, int mode, int speed)
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{
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struct imxspi_softc *sc = arg;
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uint32_t div_cnt = 0;
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uint32_t div;
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uint32_t contrl = 0;
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uint32_t config = 0;
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div = (sc->sc_freq + (speed - 1)) / speed;
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for (div_cnt = 0; div > 0; div_cnt++)
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div >>= 1;
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if (div_cnt >= 15)
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div_cnt = 15;
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contrl = READ_REG(sc, CONREG);
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contrl |= __SHIFTIN(div_cnt, ECSPI_CON_DIV);
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contrl |= __SHIFTIN(slave, ECSPI_CON_CS);
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contrl |= __SHIFTIN(__BIT(slave), ECSPI_CON_MODE);
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WRITE_REG(sc, CONREG, contrl);
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config = bus_space_read_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG);
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config &= ~(__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL) |
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__SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA));
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switch (mode) {
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case SPI_MODE_0:
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/* CPHA = 0, CPOL = 0 */
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break;
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case SPI_MODE_1:
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/* CPHA = 1, CPOL = 0 */
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config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);
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break;
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case SPI_MODE_2:
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/* CPHA = 0, CPOL = 1 */
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config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);
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break;
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case SPI_MODE_3:
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/* CPHA = 1, CPOL = 1 */
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config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_PHA);
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config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SCLK_POL);
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break;
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default:
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return EINVAL;
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}
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config |= __SHIFTIN(__BIT(slave), ECSPI_CONFIG_SSB_CTL);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, ECSPI_CONFIGREG, config);
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DPRINTFN(3, ("%s: slave %d mode %d speed %d\n",
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__func__, slave, mode, speed));
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return 0;
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}
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void
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imxspi_send(struct imxspi_softc *sc)
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{
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uint32_t data;
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struct spi_chunk *chunk;
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/* fill the fifo */
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while ((chunk = sc->sc_wchunk) != NULL) {
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while (chunk->chunk_wresid) {
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/* transmit fifo full? */
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if (READ_REG(sc, STATREG) & IMXSPI(STAT_TF))
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return;
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if (chunk->chunk_wptr) {
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data = *chunk->chunk_wptr;
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chunk->chunk_wptr++;
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} else {
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data = 0xff;
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}
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chunk->chunk_wresid--;
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WRITE_REG(sc, TXDATA, data);
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}
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/* advance to next transfer */
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sc->sc_wchunk = sc->sc_wchunk->chunk_next;
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}
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if (!(READ_REG(sc, STATREG) & IMXSPI(INTR_TE_EN)))
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WRITE_REG(sc, CONREG, READ_REG(sc, CONREG) | IMXSPI(CON_XCH));
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}
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void
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imxspi_recv(struct imxspi_softc *sc)
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{
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uint32_t data;
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struct spi_chunk *chunk;
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while ((chunk = sc->sc_rchunk) != NULL) {
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while (chunk->chunk_rresid) {
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/* rx fifo empty? */
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if ((!(READ_REG(sc, STATREG) & IMXSPI(STAT_RR))))
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return;
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/* collect rx data */
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data = READ_REG(sc, RXDATA);
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if (chunk->chunk_rptr) {
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*chunk->chunk_rptr = data & 0xff;
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chunk->chunk_rptr++;
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}
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chunk->chunk_rresid--;
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}
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/* advance next to next transfer */
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sc->sc_rchunk = sc->sc_rchunk->chunk_next;
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}
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}
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void
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imxspi_sched(struct imxspi_softc *sc)
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{
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struct spi_transfer *st;
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uint32_t chipselect;
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while ((st = spi_transq_first(&sc->sc_q)) != NULL) {
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/* remove the item */
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spi_transq_dequeue(&sc->sc_q);
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/* note that we are working on it */
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sc->sc_transfer = st;
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/* chip slect */
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if (sc->sc_tag->spi_cs_enable != NULL)
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sc->sc_tag->spi_cs_enable(sc->sc_tag->cookie,
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st->st_slave);
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/*chip slect*/
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chipselect = READ_REG(sc, CONREG);
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chipselect &= ~IMXSPI(CON_CS);
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chipselect |= __SHIFTIN(st->st_slave, IMXSPI(CON_CS));
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WRITE_REG(sc, CONREG, chipselect);
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delay(1);
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/* setup chunks */
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sc->sc_rchunk = sc->sc_wchunk = st->st_chunks;
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/* now kick the master start to get the chip running */
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imxspi_send(sc);
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sc->sc_running = TRUE;
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return;
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}
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DPRINTFN(2, ("%s: nothing to do anymore\n", __func__));
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sc->sc_running = FALSE;
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}
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void
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imxspi_done(struct imxspi_softc *sc, int err)
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{
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struct spi_transfer *st;
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/* called from interrupt handler */
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if ((st = sc->sc_transfer) != NULL) {
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if (sc->sc_tag->spi_cs_disable != NULL)
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sc->sc_tag->spi_cs_disable(sc->sc_tag->cookie,
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st->st_slave);
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sc->sc_transfer = NULL;
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spi_done(st, err);
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}
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/* make sure we clear these bits out */
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sc->sc_wchunk = sc->sc_rchunk = NULL;
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imxspi_sched(sc);
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}
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static int
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imxspi_intr(void *arg)
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{
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struct imxspi_softc *sc = arg;
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uint32_t intr, sr;
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int err = 0;
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if ((intr = READ_REG(sc, INTREG)) == 0) {
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/* interrupts are not enabled, get out */
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DPRINTFN(4, ("%s: interrupts are not enabled\n", __func__));
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return 0;
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}
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sr = READ_REG(sc, STATREG);
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if (!(sr & intr)) {
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/* interrupt did not happen, get out */
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DPRINTFN(3, ("%s: interrupts did not happen\n", __func__));
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return 0;
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}
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/* Transfer Conplete? */
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if (sr & IMXSPI(INTR_TC_EN)) {
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/* complete TX */
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imxspi_send(sc);
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}
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/* RXFIFO ready */
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if (sr & IMXSPI(INTR_RR_EN)) {
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imxspi_recv(sc);
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if (sc->sc_wchunk == NULL && sc->sc_rchunk == NULL)
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imxspi_done(sc, err);
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}
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/* status register clear */
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WRITE_REG(sc, STATREG, sr);
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return 1;
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}
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int
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imxspi_transfer(void *arg, struct spi_transfer *st)
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{
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struct imxspi_softc *sc = arg;
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int s;
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/* make sure we select the right chip */
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s = splbio();
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spi_transq_enqueue(&sc->sc_q, st);
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if (sc->sc_running == FALSE)
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imxspi_sched(sc);
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splx(s);
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return 0;
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}
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