426 lines
9.9 KiB
C
426 lines
9.9 KiB
C
/* $Id: imx23_apbdma.c,v 1.4 2015/01/10 12:13:00 jmcneill Exp $ */
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/*
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Petri Laakso.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/mutex.h>
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#include <sys/kmem.h>
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#include <sys/systm.h>
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#include <arm/imx/imx23_apbdma.h>
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#include <arm/imx/imx23_apbdmareg.h>
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#include <arm/imx/imx23_apbdmavar.h>
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#include <arm/imx/imx23_apbhdmareg.h>
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#include <arm/imx/imx23_apbxdmareg.h>
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#include <arm/imx/imx23var.h>
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static int apbdma_match(device_t, cfdata_t, void *);
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static void apbdma_attach(device_t, device_t, void *);
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static int apbdma_activate(device_t, enum devact);
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CFATTACH_DECL3_NEW(apbdma,
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sizeof(struct apbdma_softc),
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apbdma_match,
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apbdma_attach,
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NULL,
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apbdma_activate,
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NULL,
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NULL,
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0);
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static void apbdma_reset(struct apbdma_softc *);
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static void apbdma_init(struct apbdma_softc *);
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#define DMA_RD(sc, reg) \
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg))
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#define DMA_WR(sc, reg, val) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg), (val))
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#define APBDMA_SOFT_RST_LOOP 455 /* At least 1 us ... */
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static int
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apbdma_match(device_t parent, cfdata_t match, void *aux)
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{
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struct apb_attach_args *aa = aux;
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if (aa->aa_addr == HW_APBHDMA_BASE && aa->aa_size == HW_APBHDMA_SIZE)
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return 1;
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if (aa->aa_addr == HW_APBXDMA_BASE && aa->aa_size == HW_APBXDMA_SIZE)
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return 1;
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return 0;
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}
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static void
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apbdma_attach(device_t parent, device_t self, void *aux)
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{
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struct apb_attach_args *aa = aux;
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struct apbdma_softc *sc = device_private(self);
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struct apb_softc *sc_parent = device_private(parent);
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static u_int apbdma_attached = 0;
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if ((strncmp(device_xname(parent), "apbh", 4) == 0) &&
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(apbdma_attached & F_APBH_DMA))
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return;
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if ((strncmp(device_xname(parent), "apbx", 4) == 0) &&
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(apbdma_attached & F_APBX_DMA))
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return;
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sc->sc_dev = self;
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sc->sc_iot = aa->aa_iot;
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sc->sc_dmat = aa->aa_dmat;
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if (bus_space_map(sc->sc_iot,
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aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh)) {
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aprint_error_dev(sc->sc_dev, "unable to map bus space\n");
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return;
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}
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if (strncmp(device_xname(parent), "apbh", 4) == 0)
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sc->flags = F_APBH_DMA;
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if (strncmp(device_xname(parent), "apbx", 4) == 0)
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sc->flags = F_APBX_DMA;
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apbdma_reset(sc);
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apbdma_init(sc);
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if (sc->flags & F_APBH_DMA)
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apbdma_attached |= F_APBH_DMA;
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if (sc->flags & F_APBX_DMA)
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apbdma_attached |= F_APBX_DMA;
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sc_parent->dmac = self;
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/* Initialize mutex to control concurrent access from the drivers. */
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
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if (sc->flags & F_APBH_DMA)
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aprint_normal(": APBH DMA\n");
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else if (sc->flags & F_APBX_DMA)
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aprint_normal(": APBX DMA\n");
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else
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panic("dma flag missing!\n");
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return;
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}
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static int
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apbdma_activate(device_t self, enum devact act)
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{
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return EOPNOTSUPP;
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}
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/*
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* Reset the APB{H,X}DMA block.
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*
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* Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block"
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*/
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static void
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apbdma_reset(struct apbdma_softc *sc)
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{
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unsigned int loop;
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/*
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* Prepare for soft-reset by making sure that SFTRST is not currently
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* asserted. Also clear CLKGATE so we can wait for its assertion below.
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*/
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DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_SFTRST);
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/* Wait at least a microsecond for SFTRST to deassert. */
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loop = 0;
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while ((DMA_RD(sc, HW_APB_CTRL0) & HW_APB_CTRL0_SFTRST) ||
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(loop < APBDMA_SOFT_RST_LOOP))
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loop++;
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/* Clear CLKGATE so we can wait for its assertion below. */
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DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_CLKGATE);
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/* Soft-reset the block. */
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DMA_WR(sc, HW_APB_CTRL0_SET, HW_APB_CTRL0_SFTRST);
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/* Wait until clock is in the gated state. */
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while (!(DMA_RD(sc, HW_APB_CTRL0) & HW_APB_CTRL0_CLKGATE));
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/* Bring block out of reset. */
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DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_SFTRST);
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loop = 0;
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while ((DMA_RD(sc, HW_APB_CTRL0) & HW_APB_CTRL0_SFTRST) ||
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(loop < APBDMA_SOFT_RST_LOOP))
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loop++;
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DMA_WR(sc, HW_APB_CTRL0_CLR, HW_APB_CTRL0_CLKGATE);
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/* Wait until clock is in the NON-gated state. */
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while (DMA_RD(sc, HW_APB_CTRL0) & HW_APB_CTRL0_CLKGATE);
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return;
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}
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/*
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* Initialize APB{H,X}DMA block.
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*/
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static void
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apbdma_init(struct apbdma_softc *sc)
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{
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if (sc->flags & F_APBH_DMA) {
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DMA_WR(sc, HW_APBH_CTRL0_SET, HW_APBH_CTRL0_AHB_BURST8_EN);
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DMA_WR(sc, HW_APBH_CTRL0_SET, HW_APBH_CTRL0_APB_BURST4_EN);
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}
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return;
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}
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/*
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* Chain DMA commands together.
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*
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* Set src->next point to trg's physical DMA mapped address.
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*/
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void
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apbdma_cmd_chain(apbdma_command_t src, apbdma_command_t trg, void *buf,
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bus_dmamap_t dmap)
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{
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int i;
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bus_size_t daddr;
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bus_addr_t trg_offset;
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trg_offset = (bus_addr_t)trg - (bus_addr_t)buf;
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daddr = 0;
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for (i = 0; i < dmap->dm_nsegs; i++) {
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daddr += dmap->dm_segs[i].ds_len;
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if (trg_offset < daddr) {
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src->next = (void *)(dmap->dm_segs[i].ds_addr +
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(trg_offset - (daddr - dmap->dm_segs[i].ds_len)));
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break;
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}
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}
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return;
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}
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/*
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* Set DMA command buffer.
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*
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* Set cmd->buffer point to physical DMA address at offset in DMA map.
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*/
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void
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apbdma_cmd_buf(apbdma_command_t cmd, bus_addr_t offset, bus_dmamap_t dmap)
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{
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int i;
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bus_size_t daddr;
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daddr = 0;
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for (i = 0; i < dmap->dm_nsegs; i++) {
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daddr += dmap->dm_segs[i].ds_len;
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if (offset < daddr) {
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cmd->buffer = (void *)(dmap->dm_segs[i].ds_addr +
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(offset - (daddr - dmap->dm_segs[i].ds_len)));
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break;
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}
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}
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return;
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}
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/*
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* Initialize DMA channel.
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*/
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void
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apbdma_chan_init(struct apbdma_softc *sc, unsigned int channel)
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{
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mutex_enter(&sc->sc_lock);
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/* Enable CMDCMPLT_IRQ. */
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DMA_WR(sc, HW_APB_CTRL1_SET, (1<<channel)<<16);
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mutex_exit(&sc->sc_lock);
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return;
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}
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/*
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* Set command chain for DMA channel.
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*/
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#define HW_APB_CHN_NXTCMDAR(base, channel) (base + (0x70 * channel))
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void
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apbdma_chan_set_chain(struct apbdma_softc *sc, unsigned int channel,
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bus_dmamap_t dmap)
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{
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uint32_t reg;
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if (sc->flags & F_APBH_DMA)
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reg = HW_APB_CHN_NXTCMDAR(HW_APBH_CH0_NXTCMDAR, channel);
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else
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reg = HW_APB_CHN_NXTCMDAR(HW_APBX_CH0_NXTCMDAR, channel);
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mutex_enter(&sc->sc_lock);
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DMA_WR(sc, reg, dmap->dm_segs[0].ds_addr);
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mutex_exit(&sc->sc_lock);
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return;
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}
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/*
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* Initiate DMA transfer.
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*/
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#define HW_APB_CHN_SEMA(base, channel) (base + (0x70 * channel))
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void
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apbdma_run(struct apbdma_softc *sc, unsigned int channel)
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{
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uint32_t reg;
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uint8_t val;
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if (sc->flags & F_APBH_DMA) {
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reg = HW_APB_CHN_SEMA(HW_APBH_CH0_SEMA, channel);
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val = __SHIFTIN(1, HW_APBH_CH0_SEMA_INCREMENT_SEMA);
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} else {
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reg = HW_APB_CHN_SEMA(HW_APBX_CH0_SEMA, channel);
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val = __SHIFTIN(1, HW_APBX_CH0_SEMA_INCREMENT_SEMA);
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}
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mutex_enter(&sc->sc_lock);
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DMA_WR(sc, reg, val);
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mutex_exit(&sc->sc_lock);
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return;
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}
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/*
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* Acknowledge command complete IRQ.
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*/
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void
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apbdma_ack_intr(struct apbdma_softc *sc, unsigned int channel)
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{
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mutex_enter(&sc->sc_lock);
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if (sc->flags & F_APBH_DMA) {
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DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<channel));
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} else {
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DMA_WR(sc, HW_APB_CTRL1_CLR, (1<<channel));
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}
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mutex_exit(&sc->sc_lock);
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return;
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}
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/*
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* Acknowledge error IRQ.
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*/
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void
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apbdma_ack_error_intr(struct apbdma_softc *sc, unsigned int channel)
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{
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mutex_enter(&sc->sc_lock);
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DMA_WR(sc, HW_APB_CTRL2_CLR, (1<<channel));
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mutex_exit(&sc->sc_lock);
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return;
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}
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/*
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* Return reason for the IRQ.
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*/
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unsigned int
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apbdma_intr_status(struct apbdma_softc *sc, unsigned int channel)
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{
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unsigned int reason;
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reason = 0;
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mutex_enter(&sc->sc_lock);
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/* Check if this was command complete IRQ. */
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if (DMA_RD(sc, HW_APB_CTRL1) & (1<<channel))
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reason = DMA_IRQ_CMDCMPLT;
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/* Check if error was set. */
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if (DMA_RD(sc, HW_APB_CTRL2) & (1<<channel)) {
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if (DMA_RD(sc, HW_APB_CTRL2) & (1<<channel)<<16)
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reason = DMA_IRQ_BUS_ERROR;
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else
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reason = DMA_IRQ_TERM;
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}
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mutex_exit(&sc->sc_lock);
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return reason;
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}
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/*
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* Reset DMA channel.
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* Use only for devices on APBH bus.
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*/
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void
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apbdma_chan_reset(struct apbdma_softc *sc, unsigned int channel)
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{
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mutex_enter(&sc->sc_lock);
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if (sc->flags & F_APBH_DMA) {
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DMA_WR(sc, HW_APB_CTRL0_SET,
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__SHIFTIN((1<<channel), HW_APBH_CTRL0_RESET_CHANNEL));
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while(DMA_RD(sc, HW_APB_CTRL0) & HW_APBH_CTRL0_RESET_CHANNEL);
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} else {
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DMA_WR(sc, HW_APBX_CHANNEL_CTRL_SET,
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__SHIFTIN((1<<channel), HW_APBH_CTRL0_RESET_CHANNEL));
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while(DMA_RD(sc, HW_APBX_CHANNEL_CTRL) & (1<<channel));
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}
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mutex_exit(&sc->sc_lock);
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return;
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}
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void
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apbdma_wait(struct apbdma_softc *sc, unsigned int channel)
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{
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mutex_enter(&sc->sc_lock);
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if (sc->flags & F_APBH_DMA) {
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while (DMA_RD(sc, HW_APB_CHN_SEMA(HW_APBH_CH0_SEMA, channel)) & HW_APBH_CH0_SEMA_PHORE)
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;
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} else {
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while (DMA_RD(sc, HW_APB_CHN_SEMA(HW_APBX_CH0_SEMA, channel)) & HW_APBX_CH0_SEMA_PHORE)
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;
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}
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mutex_exit(&sc->sc_lock);
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}
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