441 lines
11 KiB
C
441 lines
11 KiB
C
/* $NetBSD: pxg.c,v 1.15 2003/06/29 22:30:53 fvdl Exp $ */
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/*-
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* Copyright (c) 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for DEC PixelStamp graphics accelerators with onboard SRAM and
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* Intel i860 co-processor (PMAG-D, E and F).
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pxg.c,v 1.15 2003/06/29 22:30:53 fvdl Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/callout.h>
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#include <sys/proc.h>
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#if defined(pmax)
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#include <mips/cpuregs.h>
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#elif defined(alpha)
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#include <alpha/alpha_cpu.h>
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#endif
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <dev/cons.h>
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#include <dev/wscons/wsconsio.h>
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#include <dev/wscons/wsdisplayvar.h>
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#include <dev/ic/bt459reg.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/sticreg.h>
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#include <dev/tc/sticio.h>
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#include <dev/tc/sticvar.h>
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#include <dev/tc/pxgvar.h>
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#define PXG_STIC_POLL_OFFSET 0x000000 /* STIC DMA poll space */
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#define PXG_STAMP_OFFSET 0x0c0000 /* pixelstamp space on STIC */
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#define PXG_STIC_OFFSET 0x180000 /* STIC registers */
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#define PXG_SRAM_OFFSET 0x200000 /* 128 or 256kB of SRAM */
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#define PXG_HOST_INTR_OFFSET 0x280000 /* i860 host interrupt */
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#define PXG_COPROC_INTR_OFFSET 0x2c0000 /* i860 coprocessor interrupt */
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#define PXG_VDAC_OFFSET 0x300000 /* VDAC registers (bt459) */
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#define PXG_VDAC_RESET_OFFSET 0x340000 /* VDAC reset register */
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#define PXG_ROM_OFFSET 0x380000 /* ROM code */
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#define PXG_I860_START_OFFSET 0x380000 /* i860 start register */
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#define PXG_I860_RESET_OFFSET 0x3c0000 /* i860 stop register */
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void pxg_attach(struct device *, struct device *, void *);
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int pxg_intr(void *);
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int pxg_match(struct device *, struct cfdata *, void *);
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void pxg_init(struct stic_info *);
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int pxg_ioctl(struct stic_info *, u_long, caddr_t, int, struct proc *);
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u_int32_t *pxg_pbuf_get(struct stic_info *);
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int pxg_pbuf_post(struct stic_info *, u_int32_t *);
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int pxg_probe_planes(struct stic_info *);
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int pxg_probe_sram(struct stic_info *);
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void pxg_cnattach(tc_addr_t);
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struct pxg_softc {
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struct device pxg_dv;
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struct stic_info *pxg_si;
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};
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CFATTACH_DECL(pxg, sizeof(struct pxg_softc),
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pxg_match, pxg_attach, NULL, NULL);
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static const char *pxg_types[] = {
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"PMAG-DA ",
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"PMAG-FA ",
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"PMAG-FB ",
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"PMAGB-FA",
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"PMAGB-FB",
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};
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int
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pxg_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct tc_attach_args *ta;
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int i;
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ta = aux;
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for (i = 0; i < sizeof(pxg_types) / sizeof(pxg_types[0]); i++)
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if (strncmp(pxg_types[i], ta->ta_modname, TC_ROM_LLEN) == 0)
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return (1);
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return (0);
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}
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void
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pxg_attach(struct device *parent, struct device *self, void *aux)
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{
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struct stic_info *si;
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struct tc_attach_args *ta;
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struct pxg_softc *pxg;
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int console;
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pxg = (struct pxg_softc *)self;
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ta = (struct tc_attach_args *)aux;
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if (ta->ta_addr == stic_consinfo.si_slotbase) {
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si = &stic_consinfo;
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console = 1;
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} else {
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if (stic_consinfo.si_slotbase == NULL)
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si = &stic_consinfo;
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else {
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si = malloc(sizeof(*si), M_DEVBUF, M_NOWAIT|M_ZERO);
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}
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si->si_slotbase = ta->ta_addr;
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pxg_init(si);
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console = 0;
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}
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pxg->pxg_si = si;
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si->si_dv = self;
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tc_intr_establish(parent, ta->ta_cookie, IPL_TTY, pxg_intr, si);
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printf(": %d plane, %dx%d stamp, %dkB SRAM\n", si->si_depth,
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si->si_stampw, si->si_stamph, (int)si->si_buf_size >> 10);
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stic_attach(self, si, console);
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#ifdef notyet
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/* Load the co-processor "firmware". */
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for (i = 0; i < sizeof(pxg_fwsegs) / sizeof(pxg_fwsegs[0]); i++)
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pxg_load_fwseg(si, &pxg_fwsegs[i]);
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/* Start the i860. */
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si->si_slotbase[PXG_I860_START_OFFSET >> 2] = 1;
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tc_wmb();
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tc_syncbus();
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DELAY(40000);
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#endif
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}
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void
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pxg_cnattach(tc_addr_t addr)
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{
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struct stic_info *si;
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si = &stic_consinfo;
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si->si_slotbase = addr;
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pxg_init(si);
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stic_cnattach(si);
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}
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void
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pxg_init(struct stic_info *si)
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{
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volatile u_int32_t *slot;
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caddr_t kva;
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kva = (caddr_t)si->si_slotbase;
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si->si_vdac = (u_int32_t *)(kva + PXG_VDAC_OFFSET);
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si->si_vdac_reset = (u_int32_t *)(kva + PXG_VDAC_RESET_OFFSET);
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si->si_stic = (volatile struct stic_regs *)(kva + PXG_STIC_OFFSET);
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si->si_stamp = (u_int32_t *)(kva + PXG_STAMP_OFFSET);
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si->si_buf = (u_int32_t *)(kva + PXG_SRAM_OFFSET);
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si->si_buf_phys = STIC_KSEG_TO_PHYS(si->si_buf);
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si->si_buf_size = pxg_probe_sram(si);
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si->si_disptype = WSDISPLAY_TYPE_PXG;
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si->si_sxc = (volatile struct stic_xcomm *)si->si_buf;
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si->si_pbuf_get = pxg_pbuf_get;
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si->si_pbuf_post = pxg_pbuf_post;
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si->si_ioctl = pxg_ioctl;
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/* Disable the co-processor. */
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slot = (volatile u_int32_t *)kva;
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slot[PXG_I860_RESET_OFFSET >> 2] = 0;
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tc_wmb();
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slot[PXG_HOST_INTR_OFFSET >> 2] = 0;
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tc_wmb();
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tc_syncbus();
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DELAY(40000);
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/* XXX Check for a second PixelStamp. */
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if (((si->si_stic->sr_modcl & 0x600) >> 9) > 1)
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si->si_depth = 24;
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else
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si->si_depth = pxg_probe_planes(si);
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stic_init(si);
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}
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int
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pxg_probe_sram(struct stic_info *si)
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{
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volatile u_int32_t *a, *b;
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a = (volatile u_int32_t *)si->si_slotbase + (PXG_SRAM_OFFSET >> 2);
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b = a + (0x20000 >> 2);
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*a = 4321;
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*b = 1234;
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tc_mb();
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return ((*a == *b) ? 0x20000 : 0x40000);
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}
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int
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pxg_probe_planes(struct stic_info *si)
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{
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volatile u_int32_t *vdac;
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int id;
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/*
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* For the visible framebuffer (# 0), we can cheat and use the VDAC
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* ID.
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*/
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vdac = si->si_vdac;
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vdac[BT459_REG_ADDR_LOW] = (BT459_IREG_ID & 0xff) |
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((BT459_IREG_ID & 0xff) << 8) | ((BT459_IREG_ID & 0xff) << 16);
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vdac[BT459_REG_ADDR_HIGH] = ((BT459_IREG_ID & 0xff00) >> 8) |
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(BT459_IREG_ID & 0xff00) | ((BT459_IREG_ID & 0xff00) << 8);
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tc_mb();
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id = vdac[BT459_REG_IREG_DATA] & 0x00ffffff;
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/* 3 VDACs */
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if (id == 0x004a4a4a)
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return (24);
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/* 1 VDAC */
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if ((id & 0xff0000) == 0x4a0000 || (id & 0x00ff00) == 0x004a00 ||
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(id & 0x0000ff) == 0x00004a)
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return (8);
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/* XXX Assume 8 planes. */
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printf("pxg_probe_planes: invalid VDAC ID %x\n", id);
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return (8);
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}
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int
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pxg_intr(void *cookie)
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{
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#ifdef notyet
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struct stic_info *si;
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volatile struct stic_regs *sr;
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volatile u_int32_t *hi;
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u_int32_t state;
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int it;
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si = cookie;
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sr = si->si_stic;
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state = sr->sr_ipdvint;
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hi = (volatile u_int32_t *)si->si_slotbase +
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(PXG_HOST_INTR_OFFSET / sizeof(u_int32_t));
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/* Clear the interrupt condition */
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it = hi[0] & 15;
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hi[0] = 0;
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tc_wmb();
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hi[2] = 0;
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tc_wmb();
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switch (it) {
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case 3:
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sr->sr_ipdvint = STIC_INT_V_WE | STIC_INT_V_EN;
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tc_wmb();
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stic_flush(si);
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break;
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}
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#else
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printf("pxg_intr: how did this happen?\n");
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#endif
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return (1);
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}
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u_int32_t *
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pxg_pbuf_get(struct stic_info *si)
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{
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u_long off;
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si->si_pbuf_select ^= STIC_PACKET_SIZE;
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off = si->si_pbuf_select + STIC_XCOMM_SIZE;
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return ((u_int32_t *)((caddr_t)si->si_buf + off));
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}
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int
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pxg_pbuf_post(struct stic_info *si, u_int32_t *buf)
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{
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volatile u_int32_t *poll, junk;
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volatile struct stic_regs *sr;
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u_long v;
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int c;
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sr = si->si_stic;
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/* Get address of poll register for this buffer. */
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v = ((u_long)buf - (u_long)si->si_buf) >> 9;
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poll = (volatile u_int32_t *)((caddr_t)si->si_slotbase + v);
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/*
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* Read the poll register and make sure the stamp wants to accept
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* our packet. This read will initiate the DMA. Don't wait for
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* ever, just in case something's wrong.
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*/
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tc_mb();
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for (c = STAMP_RETRIES; c != 0; c--) {
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if ((sr->sr_ipdvint & STIC_INT_P) != 0) {
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sr->sr_ipdvint = STIC_INT_P_WE;
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tc_wmb();
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junk = *poll;
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return (0);
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}
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DELAY(STAMP_DELAY);
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}
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/* STIC has lost the plot, punish it. */
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stic_reset(si);
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return (-1);
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}
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int
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pxg_ioctl(struct stic_info *si, u_long cmd, caddr_t data, int flag,
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struct proc *p)
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{
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struct stic_xinfo *sxi;
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volatile u_int32_t *ptr;
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int rv, s;
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switch (cmd) {
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case STICIO_START860:
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case STICIO_RESET860:
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if ((rv = suser(p->p_ucred, &p->p_acflag)) != 0)
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return (rv);
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if (si->si_dispmode != WSDISPLAYIO_MODE_MAPPED)
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return (EBUSY);
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ptr = (volatile u_int32_t *)si->si_slotbase;
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break;
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}
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switch (cmd) {
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case STICIO_START860:
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s = spltty();
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ptr[PXG_I860_START_OFFSET >> 2] = 1;
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tc_wmb();
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splx(s);
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rv = 0;
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break;
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case STICIO_RESET860:
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s = spltty();
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ptr[PXG_I860_RESET_OFFSET >> 2] = 0;
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tc_wmb();
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splx(s);
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rv = 0;
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break;
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case STICIO_GXINFO:
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sxi = (struct stic_xinfo *)data;
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sxi->sxi_unit = si->si_unit;
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sxi->sxi_stampw = si->si_stampw;
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sxi->sxi_stamph = si->si_stamph;
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sxi->sxi_buf_size = si->si_buf_size;
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sxi->sxi_buf_phys = 0;
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sxi->sxi_buf_pktoff = STIC_XCOMM_SIZE;
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sxi->sxi_buf_pktcnt = 2;
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sxi->sxi_buf_imgoff = STIC_XCOMM_SIZE + STIC_PACKET_SIZE * 2;
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rv = 0;
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break;
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default:
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rv = EPASSTHROUGH;
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break;
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}
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return (rv);
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}
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#ifdef notyet
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void
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pxg_load_fwseg(struct stic_info *si, struct pxg_fwseg *pfs)
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{
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const u_int32_t *src;
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u_int32_t *dst;
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u_int left, i;
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dst = (u_int32_t *)((caddr_t)si->si_buf + pfs->pfs_addr);
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src = pfs->pfs_data;
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for (left = pfs->pfs_compsize; left != 0; left -= 4) {
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if (src[0] == PXGFW_RLE_MAGIC) {
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for (i = src[2]; i != 0; i--)
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*dst++ = src[1];
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src += 3;
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} else {
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*dst++ = src[0];
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src++;
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}
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}
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if (src == NULL)
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memset(dst, 0, pfs->pfs_realsize);
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}
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#endif
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