248 lines
6.0 KiB
C
248 lines
6.0 KiB
C
/* $NetBSD: cacheops_60.h,v 1.1 1997/06/02 20:26:43 leo Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Leo Weppelman
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Invalidate entire TLB.
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*/
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void TBIA_60 __P((void));
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extern inline void
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TBIA_60()
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{
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__asm __volatile (" .word 0xf518" ); /* pflusha */
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}
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/*
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* Invalidate any TLB entry for given VA (TB Invalidate Single)
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*/
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void TBIS_60 __P((vm_offset_t));
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extern inline void
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TBIS_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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int tmp;
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__asm __volatile (" movc %1, dfc;" /* select supervisor */
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" .word 0xf508;" /* pflush a0@ */
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" moveq %3, %1;" /* select user */
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" movc %1, dfc;"
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" .word 0xf508;" /* pflush a0@ */
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" movc cacr,%1;"
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" orl %4,%1;"
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" movc %1,cacr" : "=d" (tmp) :
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"0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD),
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"i" (IC60_CABC));
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}
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/*
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* Invalidate supervisor side of TLB
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*/
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void TBIAS_60 __P((void));
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extern inline void
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TBIAS_60()
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{
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int tmp;
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/*
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* Cannot specify supervisor/user on pflusha, so we flush all
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*/
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__asm __volatile (" .word 0xf518;"
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" movc cacr,%0;"
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" orl %1,%0;"
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" movc %0,cacr" /* clear all branch cache entries */
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: "=d" (tmp) : "i" (IC60_CABC) );
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}
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/*
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* Invalidate user side of TLB
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*/
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void TBIAU_60 __P((void));
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extern inline void
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TBIAU_60()
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{
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int tmp;
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/*
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* Cannot specify supervisor/user on pflusha, so we flush all
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*/
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__asm __volatile (" .word 0xf518;"
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" movc cacr,%0;"
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" orl %1,%0;"
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" movc %0,cacr" /* clear all branch cache entries */
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: "=d" (tmp) : "i" (IC60_CUBC) );
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}
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/*
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* Invalidate instruction cache
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*/
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void ICIA_60 __P((void));
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extern inline void
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ICIA_60()
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{
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/* inva ic (also clears branch cache) */
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__asm __volatile (" .word 0xf498;");
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}
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void ICPA_60 __P((void));
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extern inline void
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ICPA_60()
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{
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/* inva ic (also clears branch cache) */
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__asm __volatile (" .word 0xf498;");
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}
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/*
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* Invalidate data cache.
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*/
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void DCIA_60 __P((void));
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extern inline void
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DCIA_60()
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{
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__asm __volatile (" .word 0xf478;"); /* cpusha dc */
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}
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void DCIS_60 __P((void));
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extern inline void
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DCIS_60()
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{
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__asm __volatile (" .word 0xf478;"); /* cpusha dc */
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}
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void DCIU_60 __P((void));
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extern inline void
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DCIU_60()
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{
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__asm __volatile (" .word 0xf478;"); /* cpusha dc */
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}
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void DCIAS_60 __P((vm_offset_t));
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extern inline void
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DCIAS_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */
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}
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void PCIA_60 __P((void));
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extern inline void
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PCIA_60()
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{
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__asm __volatile (" .word 0xf478;"); /* cpusha dc */
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}
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void DCFA_60 __P((void));
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extern inline void
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DCFA_60()
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{
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__asm __volatile (" .word 0xf478;"); /* cpusha dc */
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}
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/* invalidate instruction physical cache line */
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void ICPL_60 __P((vm_offset_t));
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extern inline void
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ICPL_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf488;" : : "a" (r_va)); /* cinvl ic,a0@ */
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}
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/* invalidate instruction physical cache page */
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void ICPP_60 __P((vm_offset_t));
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extern inline void
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ICPP_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf490;" : : "a" (r_va)); /* cinvp ic,a0@ */
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}
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/* invalidate data physical cache line */
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void DCPL_60 __P((vm_offset_t));
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extern inline void
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DCPL_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf448;" : : "a" (r_va)); /* cinvl dc,a0@ */
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}
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/* invalidate data physical cache page */
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void DCPP_60 __P((vm_offset_t));
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extern inline void
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DCPP_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf450;" : : "a" (r_va)); /* cinvp dc,a0@ */
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}
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/* invalidate data physical all */
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void DCPA_60 __P((void));
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extern inline void
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DCPA_60()
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{
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__asm __volatile (" .word 0xf458;"); /* cinva dc */
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}
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/* data cache flush line */
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void DCFL_60 __P((vm_offset_t));
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extern inline void
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DCFL_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf468;" : : "a" (r_va)); /* cpushl dc,a0@ */
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}
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/* data cache flush page */
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void DCFP_60 __P((vm_offset_t));
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extern inline void
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DCFP_60(va)
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vm_offset_t va;
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{
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register vm_offset_t r_va __asm("a0") = va;
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__asm __volatile (" .word 0xf470;" : : "a" (r_va)); /* cpushp dc,a0@ */
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}
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