1060 lines
26 KiB
C
1060 lines
26 KiB
C
/* $NetBSD: rmixl_intr.c,v 1.9 2015/06/10 22:31:00 matt Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Platform-specific interrupt support for the RMI XLP, XLR, XLS
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rmixl_intr.c,v 1.9 2015/06/10 22:31:00 matt Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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#define __INTR_PRIVATE
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#include <sys/param.h>
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#include <sys/atomic.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <mips/locore.h>
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#include <mips/rmi/rmixlreg.h>
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#include <mips/rmi/rmixlvar.h>
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#include <mips/rmi/rmixl_cpuvar.h>
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#include <mips/rmi/rmixl_intr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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//#define IOINTR_DEBUG 1
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#ifdef IOINTR_DEBUG
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int iointr_debug = IOINTR_DEBUG;
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# define DPRINTF(x) do { if (iointr_debug) printf x ; } while(0)
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#else
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# define DPRINTF(x)
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#endif
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#define RMIXL_PICREG_READ(off) \
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RMIXL_IOREG_READ(RMIXL_IO_DEV_PIC + (off))
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#define RMIXL_PICREG_WRITE(off, val) \
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RMIXL_IOREG_WRITE(RMIXL_IO_DEV_PIC + (off), (val))
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/*
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* do not clear these when acking EIRR
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* (otherwise they get lost)
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*/
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#define RMIXL_EIRR_PRESERVE_MASK \
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((MIPS_INT_MASK_5|MIPS_SOFT_INT_MASK) >> 8)
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/*
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* IRT assignments depends on the RMI chip family
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* (XLS1xx vs. XLS2xx vs. XLS3xx vs. XLS6xx)
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* use the right display string table for the CPU that's running.
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*/
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/*
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* rmixl_irtnames_xlrxxx
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* - use for XLRxxx
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*/
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static const char * const rmixl_irtnames_xlrxxx[NIRTS] = {
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"pic int 0 (watchdog)", /* 0 */
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"pic int 1 (timer0)", /* 1 */
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"pic int 2 (timer1)", /* 2 */
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"pic int 3 (timer2)", /* 3 */
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"pic int 4 (timer3)", /* 4 */
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"pic int 5 (timer4)", /* 5 */
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"pic int 6 (timer5)", /* 6 */
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"pic int 7 (timer6)", /* 7 */
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"pic int 8 (timer7)", /* 8 */
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"pic int 9 (uart0)", /* 9 */
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"pic int 10 (uart1)", /* 10 */
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"pic int 11 (i2c0)", /* 11 */
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"pic int 12 (i2c1)", /* 12 */
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"pic int 13 (pcmcia)", /* 13 */
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"pic int 14 (gpio)", /* 14 */
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"pic int 15 (hyper)", /* 15 */
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"pic int 16 (pcix)", /* 16 */
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"pic int 17 (gmac0)", /* 17 */
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"pic int 18 (gmac1)", /* 18 */
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"pic int 19 (gmac2)", /* 19 */
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"pic int 20 (gmac3)", /* 20 */
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"pic int 21 (xgs0)", /* 21 */
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"pic int 22 (xgs1)", /* 22 */
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"pic int 23 (irq23)", /* 23 */
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"pic int 24 (hyper_fatal)", /* 24 */
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"pic int 25 (bridge_aerr)", /* 25 */
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"pic int 26 (bridge_berr)", /* 26 */
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"pic int 27 (bridge_tb)", /* 27 */
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"pic int 28 (bridge_nmi)", /* 28 */
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"pic int 29 (bridge_sram_derr)",/* 29 */
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"pic int 30 (gpio_fatal)", /* 30 */
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"pic int 31 (reserved)", /* 31 */
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};
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/*
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* rmixl_irtnames_xls2xx
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* - use for XLS2xx
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*/
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static const char * const rmixl_irtnames_xls2xx[NIRTS] = {
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"pic int 0 (watchdog)", /* 0 */
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"pic int 1 (timer0)", /* 1 */
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"pic int 2 (timer1)", /* 2 */
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"pic int 3 (timer2)", /* 3 */
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"pic int 4 (timer3)", /* 4 */
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"pic int 5 (timer4)", /* 5 */
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"pic int 6 (timer5)", /* 6 */
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"pic int 7 (timer6)", /* 7 */
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"pic int 8 (timer7)", /* 8 */
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"pic int 9 (uart0)", /* 9 */
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"pic int 10 (uart1)", /* 10 */
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"pic int 11 (i2c0)", /* 11 */
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"pic int 12 (i2c1)", /* 12 */
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"pic int 13 (pcmcia)", /* 13 */
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"pic int 14 (gpio_a)", /* 14 */
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"pic int 15 (irq15)", /* 15 */
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"pic int 16 (bridge_tb)", /* 16 */
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"pic int 17 (gmac0)", /* 17 */
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"pic int 18 (gmac1)", /* 18 */
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"pic int 19 (gmac2)", /* 19 */
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"pic int 20 (gmac3)", /* 20 */
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"pic int 21 (irq21)", /* 21 */
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"pic int 22 (irq22)", /* 22 */
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"pic int 23 (pcie_link2)", /* 23 */
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"pic int 24 (pcie_link3)", /* 24 */
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"pic int 25 (bridge_err)", /* 25 */
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"pic int 26 (pcie_link0)", /* 26 */
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"pic int 27 (pcie_link1)", /* 27 */
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"pic int 28 (irq28)", /* 28 */
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"pic int 29 (pcie_err)", /* 29 */
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"pic int 30 (gpio_b)", /* 30 */
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"pic int 31 (usb)", /* 31 */
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};
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/*
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* rmixl_irtnames_xls1xx
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* - use for XLS1xx, XLS4xx-Lite
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*/
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static const char * const rmixl_irtnames_xls1xx[NIRTS] = {
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"pic int 0 (watchdog)", /* 0 */
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"pic int 1 (timer0)", /* 1 */
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"pic int 2 (timer1)", /* 2 */
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"pic int 3 (timer2)", /* 3 */
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"pic int 4 (timer3)", /* 4 */
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"pic int 5 (timer4)", /* 5 */
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"pic int 6 (timer5)", /* 6 */
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"pic int 7 (timer6)", /* 7 */
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"pic int 8 (timer7)", /* 8 */
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"pic int 9 (uart0)", /* 9 */
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"pic int 10 (uart1)", /* 10 */
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"pic int 11 (i2c0)", /* 11 */
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"pic int 12 (i2c1)", /* 12 */
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"pic int 13 (pcmcia)", /* 13 */
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"pic int 14 (gpio_a)", /* 14 */
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"pic int 15 (irq15)", /* 15 */
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"pic int 16 (bridge_tb)", /* 16 */
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"pic int 17 (gmac0)", /* 17 */
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"pic int 18 (gmac1)", /* 18 */
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"pic int 19 (gmac2)", /* 19 */
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"pic int 20 (gmac3)", /* 20 */
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"pic int 21 (irq21)", /* 21 */
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"pic int 22 (irq22)", /* 22 */
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"pic int 23 (irq23)", /* 23 */
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"pic int 24 (irq24)", /* 24 */
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"pic int 25 (bridge_err)", /* 25 */
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"pic int 26 (pcie_link0)", /* 26 */
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"pic int 27 (pcie_link1)", /* 27 */
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"pic int 28 (irq28)", /* 28 */
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"pic int 29 (pcie_err)", /* 29 */
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"pic int 30 (gpio_b)", /* 30 */
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"pic int 31 (usb)", /* 31 */
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};
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/*
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* rmixl_irtnames_xls4xx:
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* - use for XLS4xx, XLS6xx
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*/
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static const char * const rmixl_irtnames_xls4xx[NIRTS] = {
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"pic int 0 (watchdog)", /* 0 */
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"pic int 1 (timer0)", /* 1 */
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"pic int 2 (timer1)", /* 2 */
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"pic int 3 (timer2)", /* 3 */
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"pic int 4 (timer3)", /* 4 */
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"pic int 5 (timer4)", /* 5 */
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"pic int 6 (timer5)", /* 6 */
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"pic int 7 (timer6)", /* 7 */
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"pic int 8 (timer7)", /* 8 */
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"pic int 9 (uart0)", /* 9 */
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"pic int 10 (uart1)", /* 10 */
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"pic int 11 (i2c0)", /* 11 */
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"pic int 12 (i2c1)", /* 12 */
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"pic int 13 (pcmcia)", /* 13 */
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"pic int 14 (gpio_a)", /* 14 */
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"pic int 15 (irq15)", /* 15 */
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"pic int 16 (bridge_tb)", /* 16 */
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"pic int 17 (gmac0)", /* 17 */
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"pic int 18 (gmac1)", /* 18 */
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"pic int 19 (gmac2)", /* 19 */
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"pic int 20 (gmac3)", /* 20 */
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"pic int 21 (irq21)", /* 21 */
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"pic int 22 (irq22)", /* 22 */
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"pic int 23 (irq23)", /* 23 */
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"pic int 24 (irq24)", /* 24 */
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"pic int 25 (bridge_err)", /* 25 */
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"pic int 26 (pcie_link0)", /* 26 */
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"pic int 27 (pcie_link1)", /* 27 */
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"pic int 28 (pcie_link2)", /* 28 */
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"pic int 29 (pcie_link3)", /* 29 */
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"pic int 30 (gpio_b)", /* 30 */
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"pic int 31 (usb)", /* 31 */
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};
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/*
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* rmixl_vecnames_common:
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* - use for unknown cpu implementation
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* - covers all vectors, not just IRT intrs
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*/
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static const char * const rmixl_vecnames_common[NINTRVECS] = {
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"vec 0", /* 0 */
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"vec 1", /* 1 */
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"vec 2", /* 2 */
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"vec 3", /* 3 */
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"vec 4", /* 4 */
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"vec 5", /* 5 */
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"vec 6", /* 6 */
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"vec 7", /* 7 */
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"vec 8 (ipi 0)", /* 8 */
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"vec 9 (ipi 1)", /* 9 */
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"vec 10 (ipi 2)", /* 10 */
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"vec 11 (ipi 3)", /* 11 */
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"vec 12 (ipi 4)", /* 12 */
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"vec 13 (ipi 5)", /* 13 */
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"vec 14 (ipi 6)", /* 14 */
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"vec 15 (fmn)", /* 15 */
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"vec 16", /* 16 */
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"vec 17", /* 17 */
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"vec 18", /* 18 */
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"vec 19", /* 19 */
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"vec 20", /* 20 */
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"vec 21", /* 21 */
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"vec 22", /* 22 */
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"vec 23", /* 23 */
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"vec 24", /* 24 */
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"vec 25", /* 25 */
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"vec 26", /* 26 */
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"vec 27", /* 27 */
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"vec 28", /* 28 */
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"vec 29", /* 29 */
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"vec 30", /* 30 */
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"vec 31", /* 31 */
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"vec 32", /* 32 */
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"vec 33", /* 33 */
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"vec 34", /* 34 */
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"vec 35", /* 35 */
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"vec 36", /* 36 */
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"vec 37", /* 37 */
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"vec 38", /* 38 */
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"vec 39", /* 39 */
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"vec 40", /* 40 */
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"vec 41", /* 41 */
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"vec 42", /* 42 */
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"vec 43", /* 43 */
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"vec 44", /* 44 */
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"vec 45", /* 45 */
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"vec 46", /* 46 */
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"vec 47", /* 47 */
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"vec 48", /* 48 */
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"vec 49", /* 49 */
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"vec 50", /* 50 */
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"vec 51", /* 51 */
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"vec 52", /* 52 */
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"vec 53", /* 53 */
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"vec 54", /* 54 */
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"vec 55", /* 55 */
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"vec 56", /* 56 */
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"vec 57", /* 57 */
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"vec 58", /* 58 */
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"vec 59", /* 59 */
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"vec 60", /* 60 */
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"vec 61", /* 61 */
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"vec 62", /* 63 */
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"vec 63", /* 63 */
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};
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/*
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* mask of CPUs attached
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* once they are attached, this var is read-only so mp safe
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*/
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static uint32_t cpu_present_mask;
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kmutex_t rmixl_ipi_lock __cacheline_aligned;
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/* covers RMIXL_PIC_IPIBASE */
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kmutex_t rmixl_intr_lock __cacheline_aligned;
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/* covers rest of PIC, and rmixl_intrhand[] */
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rmixl_intrhand_t rmixl_intrhand[NINTRVECS];
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#ifdef DIAGNOSTIC
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static int rmixl_pic_init_done;
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#endif
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static const char *rmixl_intr_string_xlr(int);
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static const char *rmixl_intr_string_xls(int);
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static uint32_t rmixl_irt_thread_mask(int);
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static void rmixl_irt_init(int);
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static void rmixl_irt_disestablish(int);
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static void rmixl_irt_establish(int, int, int,
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rmixl_intr_trigger_t, rmixl_intr_polarity_t);
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#ifdef MULTIPROCESSOR
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static int rmixl_send_ipi(struct cpu_info *, int);
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static int rmixl_ipi_intr(void *);
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#endif
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#if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB)
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int rmixl_intrhand_print_subr(int);
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int rmixl_intrhand_print(void);
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int rmixl_irt_print(void);
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void rmixl_ipl_eimr_map_print(void);
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#endif
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static inline u_int
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dclz(uint64_t val)
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{
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int nlz;
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asm volatile("dclz %0, %1;"
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: "=r"(nlz) : "r"(val));
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return nlz;
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}
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void
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evbmips_intr_init(void)
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{
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uint32_t r;
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KASSERT(cpu_rmixlr(mips_options.mips_cpu)
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|| cpu_rmixls(mips_options.mips_cpu));
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#ifdef DIAGNOSTIC
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if (rmixl_pic_init_done != 0)
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panic("%s: rmixl_pic_init_done %d",
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__func__, rmixl_pic_init_done);
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#endif
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mutex_init(&rmixl_ipi_lock, MUTEX_DEFAULT, IPL_HIGH);
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mutex_init(&rmixl_intr_lock, MUTEX_DEFAULT, IPL_HIGH);
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mutex_enter(&rmixl_intr_lock);
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/*
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* initialize (zero) all IRT Entries in the PIC
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*/
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for (u_int i = 0; i < NIRTS; i++) {
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rmixl_irt_init(i);
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}
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/*
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* disable watchdog NMI, timers
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*
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* XXX
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* WATCHDOG_ENB is preserved because clearing it causes
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* hang on the XLS616 (but not on the XLS408)
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*/
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r = RMIXL_PICREG_READ(RMIXL_PIC_CONTROL);
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r &= RMIXL_PIC_CONTROL_RESV|RMIXL_PIC_CONTROL_WATCHDOG_ENB;
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RMIXL_PICREG_WRITE(RMIXL_PIC_CONTROL, r);
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#ifdef DIAGNOSTIC
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rmixl_pic_init_done = 1;
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#endif
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mutex_exit(&rmixl_intr_lock);
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}
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/*
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* establish vector for mips3 count/compare clock interrupt
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* this ensures we enable in EIRR,
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* even though cpu_intr() handles the interrupt
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* note the 'mpsafe' arg here is a placeholder only
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*/
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void
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rmixl_intr_init_clk(void)
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{
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const int vec = ffs(MIPS_INT_MASK_5 >> MIPS_INT_MASK_SHIFT) - 1;
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mutex_enter(&rmixl_intr_lock);
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void *ih = rmixl_vec_establish(vec, 0, IPL_SCHED, NULL, NULL, false);
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if (ih == NULL)
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panic("%s: establish vec %d failed", __func__, vec);
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mutex_exit(&rmixl_intr_lock);
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}
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#ifdef MULTIPROCESSOR
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/*
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* establish IPI interrupt and send function
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*/
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void
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rmixl_intr_init_ipi(void)
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{
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mutex_enter(&rmixl_intr_lock);
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for (u_int ipi = 0; ipi < NIPIS; ipi++) {
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const u_int vec = RMIXL_INTRVEC_IPI + ipi;
|
|
void * const ih = rmixl_vec_establish(vec, -1, IPL_SCHED,
|
|
rmixl_ipi_intr, (void *)(uintptr_t)ipi, true);
|
|
if (ih == NULL)
|
|
panic("%s: establish ipi %d at vec %d failed",
|
|
__func__, ipi, vec);
|
|
}
|
|
|
|
mips_locoresw.lsw_send_ipi = rmixl_send_ipi;
|
|
|
|
mutex_exit(&rmixl_intr_lock);
|
|
}
|
|
#endif /* MULTIPROCESSOR */
|
|
|
|
/*
|
|
* initialize per-cpu interrupt stuff in softc
|
|
* accumulate per-cpu bits in 'cpu_present_mask'
|
|
*/
|
|
void
|
|
rmixl_intr_init_cpu(struct cpu_info *ci)
|
|
{
|
|
struct rmixl_cpu_softc *sc = (void *)ci->ci_softc;
|
|
|
|
KASSERT(sc != NULL);
|
|
|
|
for (int vec=0; vec < NINTRVECS; vec++)
|
|
evcnt_attach_dynamic(&sc->sc_vec_evcnts[vec],
|
|
EVCNT_TYPE_INTR, NULL,
|
|
device_xname(sc->sc_dev),
|
|
rmixl_intr_string(vec));
|
|
|
|
KASSERT(cpu_index(ci) < (sizeof(cpu_present_mask) * 8));
|
|
atomic_or_32((volatile uint32_t *)&cpu_present_mask, 1 << cpu_index(ci));
|
|
}
|
|
|
|
/*
|
|
* rmixl_intr_string - return pointer to display name of a PIC-based interrupt
|
|
*/
|
|
const char *
|
|
rmixl_intr_string(int vec)
|
|
{
|
|
int irt;
|
|
|
|
if (vec < 0 || vec >= NINTRVECS)
|
|
panic("%s: vec index %d out of range, max %d",
|
|
__func__, vec, NINTRVECS - 1);
|
|
|
|
if (! RMIXL_VECTOR_IS_IRT(vec))
|
|
return rmixl_vecnames_common[vec];
|
|
|
|
irt = RMIXL_VECTOR_IRT(vec);
|
|
switch(cpu_rmixl_chip_type(mips_options.mips_cpu)) {
|
|
case CIDFL_RMI_TYPE_XLR:
|
|
return rmixl_intr_string_xlr(irt);
|
|
case CIDFL_RMI_TYPE_XLS:
|
|
return rmixl_intr_string_xls(irt);
|
|
case CIDFL_RMI_TYPE_XLP:
|
|
panic("%s: RMI XLP not yet supported", __func__);
|
|
}
|
|
|
|
return "undefined"; /* appease gcc */
|
|
}
|
|
|
|
static const char *
|
|
rmixl_intr_string_xlr(int irt)
|
|
{
|
|
return rmixl_irtnames_xlrxxx[irt];
|
|
}
|
|
|
|
static const char *
|
|
rmixl_intr_string_xls(int irt)
|
|
{
|
|
const char *name;
|
|
|
|
switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
|
|
case MIPS_XLS104:
|
|
case MIPS_XLS108:
|
|
case MIPS_XLS404LITE:
|
|
case MIPS_XLS408LITE:
|
|
name = rmixl_irtnames_xls1xx[irt];
|
|
break;
|
|
case MIPS_XLS204:
|
|
case MIPS_XLS208:
|
|
name = rmixl_irtnames_xls2xx[irt];
|
|
break;
|
|
case MIPS_XLS404:
|
|
case MIPS_XLS408:
|
|
case MIPS_XLS416:
|
|
case MIPS_XLS608:
|
|
case MIPS_XLS616:
|
|
name = rmixl_irtnames_xls4xx[irt];
|
|
break;
|
|
default:
|
|
name = rmixl_vecnames_common[RMIXL_IRT_VECTOR(irt)];
|
|
break;
|
|
}
|
|
|
|
return name;
|
|
}
|
|
|
|
/*
|
|
* rmixl_irt_thread_mask
|
|
*
|
|
* given a bitmask of cpus, return a, IRT thread mask
|
|
*/
|
|
static uint32_t
|
|
rmixl_irt_thread_mask(int cpumask)
|
|
{
|
|
uint32_t irtc0;
|
|
|
|
#if defined(MULTIPROCESSOR)
|
|
#ifndef NOTYET
|
|
if (cpumask == -1)
|
|
return 1; /* XXX TMP FIXME */
|
|
#endif
|
|
|
|
/*
|
|
* discount cpus not present
|
|
*/
|
|
cpumask &= cpu_present_mask;
|
|
|
|
switch (MIPS_PRID_IMPL(mips_options.mips_cpu_id)) {
|
|
case MIPS_XLS104:
|
|
case MIPS_XLS204:
|
|
case MIPS_XLS404:
|
|
case MIPS_XLS404LITE:
|
|
irtc0 = ((cpumask >> 2) << 4) | (cpumask & __BITS(1,0));
|
|
irtc0 &= (__BITS(5,4) | __BITS(1,0));
|
|
break;
|
|
case MIPS_XLS108:
|
|
case MIPS_XLS208:
|
|
case MIPS_XLS408:
|
|
case MIPS_XLS408LITE:
|
|
case MIPS_XLS608:
|
|
irtc0 = cpumask & __BITS(7,0);
|
|
break;
|
|
case MIPS_XLS416:
|
|
case MIPS_XLS616:
|
|
irtc0 = cpumask & __BITS(15,0);
|
|
break;
|
|
default:
|
|
panic("%s: unknown cpu ID %#x\n", __func__,
|
|
mips_options.mips_cpu_id);
|
|
}
|
|
#else
|
|
irtc0 = 1;
|
|
#endif /* MULTIPROCESSOR */
|
|
|
|
return irtc0;
|
|
}
|
|
|
|
/*
|
|
* rmixl_irt_init
|
|
* - initialize IRT Entry for given index
|
|
* - unmask Thread#0 in low word (assume we only have 1 thread)
|
|
*/
|
|
static void
|
|
rmixl_irt_init(int irt)
|
|
{
|
|
KASSERT(irt < NIRTS);
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), 0); /* high word */
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), 0); /* low word */
|
|
}
|
|
|
|
/*
|
|
* rmixl_irt_disestablish
|
|
* - invalidate IRT Entry for given index
|
|
*/
|
|
static void
|
|
rmixl_irt_disestablish(int irt)
|
|
{
|
|
KASSERT(mutex_owned(&rmixl_intr_lock));
|
|
DPRINTF(("%s: irt %d, irtc1 %#x\n", __func__, irt, 0));
|
|
rmixl_irt_init(irt);
|
|
}
|
|
|
|
/*
|
|
* rmixl_irt_establish
|
|
* - construct an IRT Entry for irt and write to PIC
|
|
*/
|
|
static void
|
|
rmixl_irt_establish(int irt, int vec, int cpumask, rmixl_intr_trigger_t trigger,
|
|
rmixl_intr_polarity_t polarity)
|
|
{
|
|
uint32_t irtc1;
|
|
uint32_t irtc0;
|
|
|
|
KASSERT(mutex_owned(&rmixl_intr_lock));
|
|
|
|
if (irt >= NIRTS)
|
|
panic("%s: bad irt %d\n", __func__, irt);
|
|
|
|
if (! RMIXL_VECTOR_IS_IRT(vec))
|
|
panic("%s: bad vec %d\n", __func__, vec);
|
|
|
|
switch (trigger) {
|
|
case RMIXL_TRIG_EDGE:
|
|
case RMIXL_TRIG_LEVEL:
|
|
break;
|
|
default:
|
|
panic("%s: bad trigger %d\n", __func__, trigger);
|
|
}
|
|
|
|
switch (polarity) {
|
|
case RMIXL_POLR_RISING:
|
|
case RMIXL_POLR_HIGH:
|
|
case RMIXL_POLR_FALLING:
|
|
case RMIXL_POLR_LOW:
|
|
break;
|
|
default:
|
|
panic("%s: bad polarity %d\n", __func__, polarity);
|
|
}
|
|
|
|
/*
|
|
* XXX IRT entries are not shared
|
|
*/
|
|
KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt)) == 0);
|
|
KASSERT(RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt)) == 0);
|
|
|
|
irtc0 = rmixl_irt_thread_mask(cpumask);
|
|
|
|
irtc1 = RMIXL_PIC_IRTENTRYC1_VALID;
|
|
irtc1 |= RMIXL_PIC_IRTENTRYC1_GL; /* local */
|
|
KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0);
|
|
|
|
if (trigger == RMIXL_TRIG_LEVEL)
|
|
irtc1 |= RMIXL_PIC_IRTENTRYC1_TRG;
|
|
KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0);
|
|
|
|
if ((polarity == RMIXL_POLR_FALLING) || (polarity == RMIXL_POLR_LOW))
|
|
irtc1 |= RMIXL_PIC_IRTENTRYC1_P;
|
|
KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0);
|
|
|
|
irtc1 |= vec; /* vector in EIRR */
|
|
KASSERT((irtc1 & RMIXL_PIC_IRTENTRYC1_NMI) == 0);
|
|
|
|
/*
|
|
* write IRT Entry to PIC
|
|
*/
|
|
DPRINTF(("%s: vec %d (%#x), irt %d, irtc0 %#x, irtc1 %#x\n",
|
|
__func__, vec, vec, irt, irtc0, irtc1));
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC0(irt), irtc0); /* low word */
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_IRTENTRYC1(irt), irtc1); /* high word */
|
|
}
|
|
|
|
void *
|
|
rmixl_vec_establish(int vec, int cpumask, int ipl,
|
|
int (*func)(void *), void *arg, bool mpsafe)
|
|
{
|
|
rmixl_intrhand_t *ih;
|
|
uint64_t eimr_bit;
|
|
int s;
|
|
|
|
KASSERT(mutex_owned(&rmixl_intr_lock));
|
|
|
|
DPRINTF(("%s: vec %d cpumask %#x ipl %d func %p arg %p mpsafe %d\n",
|
|
__func__, vec, cpumask, ipl, func, arg, mpsafe));
|
|
#ifdef DIAGNOSTIC
|
|
if (rmixl_pic_init_done == 0)
|
|
panic("%s: called before evbmips_intr_init", __func__);
|
|
#endif
|
|
|
|
/*
|
|
* check args
|
|
*/
|
|
if (vec < 0 || vec >= NINTRVECS)
|
|
panic("%s: vec %d out of range, max %d",
|
|
__func__, vec, NINTRVECS - 1);
|
|
if (ipl <= 0 || ipl >= _IPL_N)
|
|
panic("%s: ipl %d out of range, min %d, max %d",
|
|
__func__, ipl, 1, _IPL_N - 1);
|
|
|
|
s = splhigh();
|
|
|
|
ih = &rmixl_intrhand[vec];
|
|
if (ih->ih_func != NULL) {
|
|
#ifdef DIAGNOSTIC
|
|
printf("%s: intrhand[%d] busy\n", __func__, vec);
|
|
#endif
|
|
splx(s);
|
|
return NULL;
|
|
}
|
|
|
|
ih->ih_arg = arg;
|
|
ih->ih_mpsafe = mpsafe;
|
|
ih->ih_vec = vec;
|
|
ih->ih_ipl = ipl;
|
|
ih->ih_cpumask = cpumask;
|
|
|
|
eimr_bit = (uint64_t)1 << vec;
|
|
for (int i=ih->ih_ipl; --i >= 0; ) {
|
|
KASSERT((ipl_eimr_map[i] & eimr_bit) == 0);
|
|
ipl_eimr_map[i] |= eimr_bit;
|
|
}
|
|
|
|
ih->ih_func = func; /* do this last */
|
|
|
|
splx(s);
|
|
|
|
return ih;
|
|
}
|
|
|
|
/*
|
|
* rmixl_intr_establish
|
|
* - used to establish an IRT-based interrupt only
|
|
*/
|
|
void *
|
|
rmixl_intr_establish(int irt, int cpumask, int ipl,
|
|
rmixl_intr_trigger_t trigger, rmixl_intr_polarity_t polarity,
|
|
int (*func)(void *), void *arg, bool mpsafe)
|
|
{
|
|
rmixl_intrhand_t *ih;
|
|
int vec;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (rmixl_pic_init_done == 0)
|
|
panic("%s: called before rmixl_pic_init_done", __func__);
|
|
#endif
|
|
|
|
/*
|
|
* check args
|
|
*/
|
|
if (irt < 0 || irt >= NIRTS)
|
|
panic("%s: irt %d out of range, max %d",
|
|
__func__, irt, NIRTS - 1);
|
|
if (ipl <= 0 || ipl >= _IPL_N)
|
|
panic("%s: ipl %d out of range, min %d, max %d",
|
|
__func__, ipl, 1, _IPL_N - 1);
|
|
|
|
vec = RMIXL_IRT_VECTOR(irt);
|
|
|
|
DPRINTF(("%s: irt %d, vec %d, ipl %d\n", __func__, irt, vec, ipl));
|
|
|
|
mutex_enter(&rmixl_intr_lock);
|
|
|
|
/*
|
|
* establish vector
|
|
*/
|
|
ih = rmixl_vec_establish(vec, cpumask, ipl, func, arg, mpsafe);
|
|
|
|
/*
|
|
* establish IRT Entry
|
|
*/
|
|
rmixl_irt_establish(irt, vec, cpumask, trigger, polarity);
|
|
|
|
mutex_exit(&rmixl_intr_lock);
|
|
|
|
return ih;
|
|
}
|
|
|
|
void
|
|
rmixl_vec_disestablish(void *cookie)
|
|
{
|
|
rmixl_intrhand_t *ih = cookie;
|
|
uint64_t eimr_bit;
|
|
|
|
KASSERT(mutex_owned(&rmixl_intr_lock));
|
|
KASSERT(ih->ih_vec < NINTRVECS);
|
|
KASSERT(ih == &rmixl_intrhand[ih->ih_vec]);
|
|
|
|
ih->ih_func = NULL; /* do this first */
|
|
|
|
eimr_bit = (uint64_t)1 << ih->ih_vec;
|
|
for (int i=ih->ih_ipl; --i >= 0; ) {
|
|
KASSERT((ipl_eimr_map[i] & eimr_bit) != 0);
|
|
ipl_eimr_map[i] ^= eimr_bit;
|
|
}
|
|
}
|
|
|
|
void
|
|
rmixl_intr_disestablish(void *cookie)
|
|
{
|
|
rmixl_intrhand_t *ih = cookie;
|
|
const int vec = ih->ih_vec;
|
|
|
|
KASSERT(vec < NINTRVECS);
|
|
KASSERT(ih == &rmixl_intrhand[vec]);
|
|
|
|
mutex_enter(&rmixl_intr_lock);
|
|
|
|
/*
|
|
* disable/invalidate the IRT Entry if needed
|
|
*/
|
|
if (RMIXL_VECTOR_IS_IRT(vec))
|
|
rmixl_irt_disestablish(vec);
|
|
|
|
/*
|
|
* disasociate from vector and free the handle
|
|
*/
|
|
rmixl_vec_disestablish(cookie);
|
|
|
|
mutex_exit(&rmixl_intr_lock);
|
|
}
|
|
|
|
void
|
|
evbmips_iointr(int ipl, vaddr_t pc, uint32_t pending)
|
|
{
|
|
struct rmixl_cpu_softc *sc = (void *)curcpu()->ci_softc;
|
|
|
|
DPRINTF(("%s: cpu%u: ipl %d, pc %#"PRIxVADDR", pending %#x\n",
|
|
__func__, cpu_number(), ipl, pc, pending));
|
|
|
|
/*
|
|
* 'pending' arg is a summary that there is something to do
|
|
* the real pending status is obtained from EIRR
|
|
*/
|
|
KASSERT(pending == MIPS_INT_MASK_1);
|
|
|
|
for (;;) {
|
|
rmixl_intrhand_t *ih;
|
|
uint64_t eirr;
|
|
uint64_t eimr;
|
|
uint64_t vecbit;
|
|
int vec;
|
|
|
|
asm volatile("dmfc0 %0, $9, 6;" : "=r"(eirr));
|
|
asm volatile("dmfc0 %0, $9, 7;" : "=r"(eimr));
|
|
|
|
#ifdef IOINTR_DEBUG
|
|
printf("%s: cpu%u: eirr %#"PRIx64", eimr %#"PRIx64", mask %#"PRIx64"\n",
|
|
__func__, cpu_number(), eirr, eimr, ipl_eimr_map[ipl-1]);
|
|
#endif /* IOINTR_DEBUG */
|
|
|
|
/*
|
|
* reduce eirr to
|
|
* - ints that are enabled at or below this ipl
|
|
* - exclude count/compare clock and soft ints
|
|
* they are handled elsewhere
|
|
*/
|
|
eirr &= ipl_eimr_map[ipl-1];
|
|
eirr &= ~ipl_eimr_map[ipl];
|
|
eirr &= ~((MIPS_INT_MASK_5 | MIPS_SOFT_INT_MASK) >> 8);
|
|
if (eirr == 0)
|
|
break;
|
|
|
|
vec = 63 - dclz(eirr);
|
|
ih = &rmixl_intrhand[vec];
|
|
vecbit = 1ULL << vec;
|
|
KASSERT (ih->ih_ipl == ipl);
|
|
KASSERT ((vecbit & eimr) == 0);
|
|
KASSERT ((vecbit & RMIXL_EIRR_PRESERVE_MASK) == 0);
|
|
|
|
/*
|
|
* ack in EIRR, and in PIC if needed,
|
|
* the irq we are about to handle
|
|
*/
|
|
rmixl_eirr_ack(eimr, vecbit, RMIXL_EIRR_PRESERVE_MASK);
|
|
if (RMIXL_VECTOR_IS_IRT(vec))
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_INTRACK,
|
|
1 << RMIXL_VECTOR_IRT(vec));
|
|
|
|
if (ih->ih_func != NULL) {
|
|
#ifdef MULTIPROCESSOR
|
|
if (ih->ih_mpsafe) {
|
|
(void)(*ih->ih_func)(ih->ih_arg);
|
|
} else {
|
|
KASSERTMSG(ipl == IPL_VM,
|
|
"%s: %s: ipl (%d) != IPL_VM for KERNEL_LOCK",
|
|
__func__, sc->sc_vec_evcnts[vec].ev_name,
|
|
ipl);
|
|
KERNEL_LOCK(1, NULL);
|
|
(void)(*ih->ih_func)(ih->ih_arg);
|
|
KERNEL_UNLOCK_ONE(NULL);
|
|
}
|
|
#else
|
|
(void)(*ih->ih_func)(ih->ih_arg);
|
|
#endif /* MULTIPROCESSOR */
|
|
}
|
|
KASSERT(ipl == ih->ih_ipl);
|
|
KASSERTMSG(curcpu()->ci_cpl >= ipl,
|
|
"%s: after %s: cpl (%d) < ipl %d",
|
|
__func__, sc->sc_vec_evcnts[vec].ev_name,
|
|
ipl, curcpu()->ci_cpl);
|
|
sc->sc_vec_evcnts[vec].ev_count++;
|
|
}
|
|
}
|
|
|
|
#ifdef MULTIPROCESSOR
|
|
static int
|
|
rmixl_send_ipi(struct cpu_info *ci, int tag)
|
|
{
|
|
const cpuid_t cpuid = ci->ci_cpuid;
|
|
uint32_t core = (uint32_t)(cpuid >> 2);
|
|
uint32_t thread = (uint32_t)(cpuid & __BITS(1,0));
|
|
uint64_t req = 1 << tag;
|
|
uint32_t r;
|
|
|
|
if (!kcpuset_isset(cpus_running, cpu_index(ci)))
|
|
return -1;
|
|
|
|
KASSERT((tag >= 0) && (tag < NIPIS));
|
|
|
|
r = (thread << RMIXL_PIC_IPIBASE_ID_THREAD_SHIFT)
|
|
| (core << RMIXL_PIC_IPIBASE_ID_CORE_SHIFT)
|
|
| (RMIXL_INTRVEC_IPI + tag);
|
|
|
|
mutex_enter(&rmixl_ipi_lock);
|
|
atomic_or_64(&ci->ci_request_ipis, req);
|
|
RMIXL_PICREG_WRITE(RMIXL_PIC_IPIBASE, r);
|
|
mutex_exit(&rmixl_ipi_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
rmixl_ipi_intr(void *arg)
|
|
{
|
|
struct cpu_info * const ci = curcpu();
|
|
const uint64_t ipi_mask = 1 << (uintptr_t)arg;
|
|
|
|
KASSERT(ci->ci_cpl >= IPL_SCHED);
|
|
KASSERT((uintptr_t)arg < NIPIS);
|
|
|
|
/* if the request is clear, it was previously processed */
|
|
if ((ci->ci_request_ipis & ipi_mask) == 0)
|
|
return 0;
|
|
|
|
atomic_or_64(&ci->ci_active_ipis, ipi_mask);
|
|
atomic_and_64(&ci->ci_request_ipis, ~ipi_mask);
|
|
|
|
ipi_process(ci, ipi_mask);
|
|
|
|
atomic_and_64(&ci->ci_active_ipis, ~ipi_mask);
|
|
|
|
return 1;
|
|
}
|
|
#endif /* MULTIPROCESSOR */
|
|
|
|
#if defined(DIAGNOSTIC) || defined(IOINTR_DEBUG) || defined(DDB)
|
|
int
|
|
rmixl_intrhand_print_subr(int vec)
|
|
{
|
|
rmixl_intrhand_t *ih = &rmixl_intrhand[vec];
|
|
printf("vec %d: func %p, arg %p, vec %d, ipl %d, mask %#x\n",
|
|
vec, ih->ih_func, ih->ih_arg, ih->ih_vec, ih->ih_ipl,
|
|
ih->ih_cpumask);
|
|
return 0;
|
|
}
|
|
int
|
|
rmixl_intrhand_print(void)
|
|
{
|
|
for (int vec=0; vec < NINTRVECS ; vec++)
|
|
rmixl_intrhand_print_subr(vec);
|
|
return 0;
|
|
}
|
|
|
|
static inline void
|
|
rmixl_irt_entry_print(u_int irt)
|
|
{
|
|
uint32_t c0, c1;
|
|
|
|
if ((irt < 0) || (irt > NIRTS))
|
|
return;
|
|
c0 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC0(irt));
|
|
c1 = RMIXL_PICREG_READ(RMIXL_PIC_IRTENTRYC1(irt));
|
|
printf("irt[%d]: %#x, %#x\n", irt, c0, c1);
|
|
}
|
|
|
|
int
|
|
rmixl_irt_print(void)
|
|
{
|
|
printf("%s:\n", __func__);
|
|
for (int irt=0; irt < NIRTS ; irt++)
|
|
rmixl_irt_entry_print(irt);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
rmixl_ipl_eimr_map_print(void)
|
|
{
|
|
printf("IPL_NONE=%d, mask %#"PRIx64"\n",
|
|
IPL_NONE, ipl_eimr_map[IPL_NONE]);
|
|
printf("IPL_SOFTCLOCK=%d, mask %#"PRIx64"\n",
|
|
IPL_SOFTCLOCK, ipl_eimr_map[IPL_SOFTCLOCK]);
|
|
printf("IPL_SOFTNET=%d, mask %#"PRIx64"\n",
|
|
IPL_SOFTNET, ipl_eimr_map[IPL_SOFTNET]);
|
|
printf("IPL_VM=%d, mask %#"PRIx64"\n",
|
|
IPL_VM, ipl_eimr_map[IPL_VM]);
|
|
printf("IPL_SCHED=%d, mask %#"PRIx64"\n",
|
|
IPL_SCHED, ipl_eimr_map[IPL_SCHED]);
|
|
printf("IPL_DDB=%d, mask %#"PRIx64"\n",
|
|
IPL_DDB, ipl_eimr_map[IPL_DDB]);
|
|
printf("IPL_HIGH=%d, mask %#"PRIx64"\n",
|
|
IPL_HIGH, ipl_eimr_map[IPL_HIGH]);
|
|
}
|
|
|
|
#endif
|