f208f36711
- realtime clock support for a2k and a3k - scsi drivers for a2091 and gvp-II controllers in a2k - working ethernet driver for a2065/ameristar lance-controllers
106 lines
4.0 KiB
C
106 lines
4.0 KiB
C
/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dmareg.h
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*/
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/* Hardware layout of the A2091 SDMAC. This also contains the
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registers for the sbic chip, but in favor of separating DMA and
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scsi, the scsi-driver doesn't make use of this dependency */
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#define v_char volatile char
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#define v_int volatile int
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#define vu_char volatile u_char
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#define vu_short volatile u_short
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#define vu_int volatile u_int
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/* This chip definition only defines the registers also present on the
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A3000 SDMAC. */
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struct sdmac {
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short ________________pad0[0x20];
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vu_short ISTR; /* Interrupt Status Register RO */
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vu_short CNTR; /* Control Register RW */
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short ________________pad1[0x1e];
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vu_int WTC; /* Word Transfer Count Register RW */
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vu_int ACR; /* Address Count Register RW */
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short ________________pad2[0x03];
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vu_short DAWR; /* DACK Width Register WO */
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char ________________pad3;
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vu_char SASR; /* sbic asr */
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char ________________pad4;
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vu_char SCMD; /* sbic data */
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short ________________pad5[0x26];
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vu_short ST_DMA; /* Start DMA Transfers RW-Strobe */
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vu_short SP_DMA; /* Stop DMA Transfers RW-Strobe */
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vu_short CINT; /* Clear Interrupts RW-Strobe */
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short ________________pad6;
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vu_short FLUSH; /* Flush FIFO RW-Strobe */
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};
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/* value to go into DAWR */
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#define DAWR_A2091 3 /* according to A3000T service-manual */
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/* bits defined for CNTR */
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#define CNTR_TCEN (1<<7) /* Terminal Count Enable */
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#define CNTR_PREST (1<<6) /* Peripheral Reset (not implemented :-((( ) */
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#define CNTR_PDMD (1<<5) /* Peripheral Device Mode Select (1=SCSI,0=XT/AT) */
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#define CNTR_INTEN (1<<4) /* Interrupt Enable */
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#define CNTR_DDIR (1<<3) /* Device Direction. 1==read from host, write to periph */
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/* bits defined for ISTR */
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#define ISTR_INTX (1<<8) /* XT/AT Interrupt pending */
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#define ISTR_INT_F (1<<7) /* Interrupt Follow */
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#define ISTR_INTS (1<<6) /* SCSI Peripheral Interrupt */
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#define ISTR_E_INT (1<<5) /* End-Of-Process Interrupt */
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#define ISTR_INT_P (1<<4) /* Interrupt Pending */
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#define ISTR_UE_INT (1<<3) /* Under-Run FIFO Error Interrupt */
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#define ISTR_OE_INT (1<<2) /* Over-Run FIFO Error Interrupt */
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#define ISTR_FF_FLG (1<<1) /* FIFO-Full Flag */
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#define ISTR_FE_FLG (1<<0) /* FIFO-Empty Flag */
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#define NDMA 1
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