265 lines
7.3 KiB
C
265 lines
7.3 KiB
C
/* $NetBSD: if_casvar.h,v 1.2 2010/01/18 18:09:22 jdc Exp $ */
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/* $OpenBSD: if_casvar.h,v 1.6 2009/06/13 12:18:58 kettenis Exp $ */
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/*
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*
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* Copyright (C) 2007 Mark Kettenis.
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IF_CASVAR_H
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#define _IF_CASVAR_H
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#include <sys/queue.h>
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#include <sys/callout.h>
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/*
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* Misc. definitions for Sun Cassini ethernet controllers.
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*/
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/*
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* Preferred page size. Cassini has a configurable page size, but
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* needs at least 8k to handle jumbo frames. This happens to be the
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* default anyway.
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*/
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#define CAS_PAGE_SIZE 8192
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/*
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* Transmit descriptor ring size. This is arbitrary, but allocate
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* enough descriptors for 64 pending transmissions and 16 segments
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* per packet.
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*/
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#define CAS_NTXSEGS 16
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#define CAS_TXQUEUELEN 64
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#define CAS_NTXDESC (CAS_TXQUEUELEN * CAS_NTXSEGS)
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#define CAS_NTXDESC_MASK (CAS_NTXDESC - 1)
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#define CAS_NEXTTX(x) ((x + 1) & CAS_NTXDESC_MASK)
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struct cas_sxd {
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struct mbuf *sd_mbuf;
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bus_dmamap_t sd_map;
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};
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/*
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* Receive descriptor ring size. We have one Rx buffer per incoming
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* packet, so this logic is a little simpler.
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*/
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#define CAS_NRXDESC 128
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#define CAS_NRXDESC_MASK (CAS_NRXDESC - 1)
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/*
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* Receive completion ring size.
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*/
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#define CAS_NRXCOMP 256
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#define CAS_NRXCOMP_MASK (CAS_NRXCOMP - 1)
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#define CAS_NEXTRX(x) ((x + 1) & CAS_NRXCOMP_MASK)
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/*
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* Control structures are DMA'd to the Cassini chip. We allocate them in
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* a single clump that maps to a single DMA segment to make several things
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* easier.
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*/
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struct cas_control_data {
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/*
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* The transmit descriptors.
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*/
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struct cas_desc ccd_txdescs[CAS_NTXDESC];
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/*
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* The receive completions.
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*/
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struct cas_comp ccd_rxcomps[CAS_NRXCOMP];
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/*
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* The receive descriptors.
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*/
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struct cas_desc ccd_rxdescs[CAS_NRXDESC];
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char ccd_unused[CAS_PAGE_SIZE - CAS_NRXDESC * 16];
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struct cas_desc ccd_rxdescs2[CAS_NRXDESC];
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};
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#define CAS_CDOFF(x) offsetof(struct cas_control_data, x)
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#define CAS_CDTXOFF(x) CAS_CDOFF(ccd_txdescs[(x)])
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#define CAS_CDRXOFF(x) CAS_CDOFF(ccd_rxdescs[(x)])
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#define CAS_CDRXOFF2(x) CAS_CDOFF(ccd_rxdescs2[(x)])
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#define CAS_CDRXCOFF(x) CAS_CDOFF(ccd_rxcomps[(x)])
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/*
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* Software state for receive jobs.
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*/
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struct cas_rxsoft {
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bus_dmamap_t rxs_dmamap; /* our DMA map */
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bus_dma_segment_t rxs_dmaseg; /* our DMA segment */
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char *rxs_kva;
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};
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enum cas_attach_stage {
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CAS_ATT_BACKEND_2 = 0
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, CAS_ATT_BACKEND_1
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, CAS_ATT_FINISHED
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, CAS_ATT_MII
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, CAS_ATT_7
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, CAS_ATT_6
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, CAS_ATT_5
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, CAS_ATT_4
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, CAS_ATT_3
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, CAS_ATT_2
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, CAS_ATT_1
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, CAS_ATT_0
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, CAS_ATT_BACKEND_0
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};
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/*
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* Software state per device.
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*/
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struct cas_softc {
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device_t sc_dev; /* generic device information */
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struct ethercom sc_ethercom; /* ethernet common data */
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struct mii_data sc_mii; /* MII media control */
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#define sc_media sc_mii.mii_media/* shorthand */
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struct callout sc_tick_ch; /* tick callout */
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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bus_size_t sc_size;
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void *sc_ih;
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pci_chipset_tag_t sc_pc;
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pci_intr_handle_t sc_handle;
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bus_dma_tag_t sc_dmatag; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dma handle */
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int sc_burst; /* DVMA burst size in effect */
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int sc_phys[2]; /* MII instance -> PHY map */
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int sc_mif_config; /* Selected MII reg setting */
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/*
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* Ring buffer DMA stuff.
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*/
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bus_dma_segment_t sc_cdseg; /* control data memory */
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int sc_cdnseg; /* number of segments */
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bus_dmamap_t sc_cddmamap; /* control data DMA map */
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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/*
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* Software state for transmit and receive descriptors.
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*/
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struct cas_sxd sc_txd[CAS_NTXDESC];
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u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons;
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struct cas_rxsoft sc_rxsoft[CAS_NRXDESC];
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struct cas_rxsoft sc_rxsoft2[CAS_NRXDESC];
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/*
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* Control data structures.
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*/
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struct cas_control_data *sc_control_data;
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#define sc_txdescs sc_control_data->ccd_txdescs
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#define sc_rxdescs sc_control_data->ccd_rxdescs
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#define sc_rxdescs2 sc_control_data->ccd_rxdescs2
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#define sc_rxcomps sc_control_data->ccd_rxcomps
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int sc_rxptr; /* next ready RX descriptor/descsoft */
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int sc_rxfifosize;
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int sc_rxdptr;
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int sc_rev;
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int sc_inited;
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int sc_debug;
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void *sc_sh; /* shutdownhook cookie */
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#if NRND > 0
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rndsource_element_t rnd_source;
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#endif
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struct evcnt sc_ev_intr;
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enum cas_attach_stage sc_att_stage;
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};
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/*
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* This maccro determines whether we have a Cassini+.
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*/
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#define CAS_PLUS(sc) (sc->sc_rev > 0x10)
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#define CAS_DMA_READ(v) le64toh(v)
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#define CAS_DMA_WRITE(v) htole64(v)
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#define CAS_CDTXADDR(sc, x) ((sc)->sc_cddma + CAS_CDTXOFF((x)))
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#define CAS_CDRXADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF((x)))
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#define CAS_CDRXADDR2(sc, x) ((sc)->sc_cddma + CAS_CDRXOFF2((x)))
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#define CAS_CDRXCADDR(sc, x) ((sc)->sc_cddma + CAS_CDRXCOFF((x)))
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#define CAS_CDTXSYNC(sc, x, n, ops) \
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do { \
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int __x, __n; \
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\
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__x = (x); \
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__n = (n); \
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\
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/* If it will wrap around, sync to the end of the ring. */ \
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if ((__x + __n) > CAS_NTXDESC) { \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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CAS_CDTXOFF(__x), sizeof(struct cas_desc) * \
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(CAS_NTXDESC - __x), (ops)); \
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__n -= (CAS_NTXDESC - __x); \
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__x = 0; \
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} \
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\
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/* Now sync whatever is left. */ \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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CAS_CDTXOFF(__x), sizeof(struct cas_desc) * __n, (ops)); \
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} while (0)
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#define CAS_CDRXSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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CAS_CDRXOFF((x)), sizeof(struct cas_desc), (ops))
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#define CAS_CDRXCSYNC(sc, x, ops) \
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bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \
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CAS_CDRXCOFF((x)), sizeof(struct cas_desc), (ops))
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#define CAS_INIT_RXDESC(sc, d, s) \
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do { \
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struct cas_rxsoft *__rxs = &sc->sc_rxsoft[(s)]; \
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struct cas_desc *__rxd = &sc->sc_rxdescs[(d)]; \
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\
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__rxd->cd_addr = \
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CAS_DMA_WRITE(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
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__rxd->cd_flags = \
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CAS_DMA_WRITE((s)); \
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CAS_CDRXSYNC((sc), (d), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
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} while (0)
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#define CAS_INTR_PCI 1
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#define CAS_INTR_REG 2
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#define ETHER_ALIGN 2
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#endif
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