216 lines
7.3 KiB
C
216 lines
7.3 KiB
C
/* $NetBSD: hd64570var.h,v 1.7 2005/12/11 12:21:26 christos Exp $ */
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/*
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* Copyright (c) 1999 Christian E. Hopps
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* Copyright (c) 1998 Vixie Enterprises
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Vixie Enterprises nor the names
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* of its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND
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* CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This software has been written for Vixie Enterprises by Michael Graff
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* <explorer@flame.org>. To learn more about Vixie Enterprises, see
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* ``http://www.vix.com''.
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*/
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#ifndef _DEV_IC_HD64570VAR_H_
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#define _DEV_IC_HD64570VAR_H_
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#include "bpfilter.h"
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#define SCA_USE_FASTQ /* use a split queue, one for fast traffic */
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#define SCA_MTU 1500 /* hard coded */
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#ifndef SCA_BSIZE
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#define SCA_BSIZE (SCA_MTU + 4) /* room for HDLC as well */
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#endif
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struct sca_softc;
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typedef struct sca_port sca_port_t;
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typedef struct sca_desc sca_desc_t;
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/*
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* device DMA descriptor
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*/
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struct sca_desc {
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u_int16_t sd_chainp; /* chain pointer */
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u_int16_t sd_bufp; /* buffer pointer (low bits) */
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u_int8_t sd_hbufp; /* buffer pointer (high bits) */
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u_int8_t sd_unused0;
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u_int16_t sd_buflen; /* total length */
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u_int8_t sd_stat; /* status */
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u_int8_t sd_unused1;
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};
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#define SCA_DESC_EOT 0x01
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#define SCA_DESC_CRC 0x04
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#define SCA_DESC_OVRN 0x08
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#define SCA_DESC_RESD 0x10
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#define SCA_DESC_ABORT 0x20
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#define SCA_DESC_SHRTFRM 0x40
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#define SCA_DESC_EOM 0x80
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#define SCA_DESC_ERRORS 0x7C
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/*
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* softc structure for each port
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*/
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struct sca_port {
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u_int msci_off; /* offset for msci address for this port */
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u_int dmac_off; /* offset of dmac address for this port */
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u_int sp_port;
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/*
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* CISCO keepalive stuff
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*/
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u_int32_t cka_lasttx;
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u_int32_t cka_lastrx;
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/*
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* clock values, clockrate = sysclock / tmc / 2^div;
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*/
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u_int8_t sp_eclock; /* enable external clock generate */
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u_int8_t sp_rxs; /* recv clock source */
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u_int8_t sp_txs; /* transmit clock source */
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u_int8_t sp_tmc; /* clock constant */
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/*
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* start of each important bit of information for transmit and
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* receive buffers.
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*
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* note: for non-DMA the phys and virtual version should be
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* the same value and should be an _offset_ from the beginning
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* of mapped memory described by sc_memt/sc_memh.
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*/
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u_int sp_ntxdesc; /* number of tx descriptors */
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u_int32_t sp_txdesc_p; /* paddress of first tx desc */
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sca_desc_t *sp_txdesc; /* vaddress of first tx desc */
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u_int32_t sp_txbuf_p; /* paddress of first tx buffer */
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u_int8_t *sp_txbuf; /* vaddress of first tx buffer */
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volatile u_int sp_txcur; /* last descriptor in chain */
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volatile u_int sp_txinuse; /* descriptors in use */
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volatile u_int sp_txstart; /* start descriptor */
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u_int sp_nrxdesc; /* number of rx descriptors */
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u_int32_t sp_rxdesc_p; /* paddress of first rx desc */
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sca_desc_t *sp_rxdesc; /* vaddress of first rx desc */
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u_int32_t sp_rxbuf_p; /* paddress of first rx buffer */
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u_int8_t *sp_rxbuf; /* vaddress of first rx buffer */
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u_int sp_rxstart; /* index of first descriptor */
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u_int sp_rxend; /* index of last descriptor */
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struct ifnet sp_if; /* the network information */
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struct ifqueue linkq; /* link-level packets are high prio */
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#ifdef SCA_USE_FASTQ
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struct ifqueue fastq; /* interactive packets */
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#endif
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struct sca_softc *sca; /* pointer to parent */
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};
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/*
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* softc structure for the chip itself
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*/
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struct sca_softc {
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struct device *sc_parent; /* our parent device, or NULL */
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int sc_numports; /* number of ports present */
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u_int32_t sc_baseclock; /* the base operating clock */
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/*
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* a callback into the parent, since the SCA chip has no control
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* over DTR, we have to make a callback into the parent, which
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* might know about DTR.
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*
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* If the function pointer is NULL, no callback is specified.
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*/
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void *sc_aux;
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void (*sc_dtr_callback)(void *, int, int);
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void (*sc_clock_callback)(void *, int, int);
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/* used to read and write the device registers */
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u_int8_t (*sc_read_1)(struct sca_softc *, u_int);
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u_int16_t (*sc_read_2)(struct sca_softc *, u_int);
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void (*sc_write_1)(struct sca_softc *, u_int, u_int8_t);
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void (*sc_write_2)(struct sca_softc *, u_int, u_int16_t);
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sca_port_t sc_ports[2];
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bus_space_tag_t sc_iot; /* io space for registers */
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bus_space_handle_t sc_ioh; /* io space for registers */
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int sc_usedma;
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union {
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struct {
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bus_space_tag_t p_memt; /* mem for non-DMA */
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bus_space_handle_t p_memh; /* mem for non-DMA */
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bus_space_handle_t p_sca_ioh[16]; /* io for sca regs */
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bus_size_t p_pagesize; /* memory page size */
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bus_size_t p_pagemask; /* memory page mask */
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u_int p_pageshift; /* memory page shift */
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bus_size_t p_npages; /* num mem pages */
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void (*p_set_page)(struct sca_softc *, bus_addr_t);
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void (*p_page_on)(struct sca_softc *);
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void (*p_page_off)(struct sca_softc *);
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} u_paged;
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struct {
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bus_dma_tag_t d_dmat; /* bus DMA tag */
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bus_dmamap_t d_dmam; /* bus DMA map */
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bus_dma_segment_t d_seg; /* bus DMA segment */
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caddr_t d_dma_addr; /* kva of segment */
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bus_size_t d_allocsize; /* size of region */
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} u_dma;
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} sc_u;
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};
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#define scu_memt sc_u.u_paged.p_memt
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#define scu_memh sc_u.u_paged.p_memh
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#define scu_sca_ioh sc_u.u_paged.p_sca_ioh
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#define scu_pagesize sc_u.u_paged.p_pagesize
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#define scu_pagemask sc_u.u_paged.p_pagemask
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#define scu_pageshift sc_u.u_paged.p_pageshift
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#define scu_npages sc_u.u_paged.p_npages
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#define scu_set_page sc_u.u_paged.p_set_page
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#define scu_page_on sc_u.u_paged.p_page_on
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#define scu_page_off sc_u.u_paged.p_page_off
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#define scu_dmat sc_u.u_dma.d_dmat
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#define scu_dmam sc_u.u_dma.d_dmam
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#define scu_seg sc_u.u_dma.d_seg
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#define scu_dma_addr sc_u.u_dma.d_dma_addr
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#define scu_allocsize sc_u.u_dma.d_allocsize
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void sca_init(struct sca_softc *);
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void sca_port_attach(struct sca_softc *, u_int);
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int sca_hardintr(struct sca_softc *);
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void sca_shutdown(struct sca_softc *);
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void sca_get_base_clock(struct sca_softc *);
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void sca_print_clock_info(struct sca_softc *);
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#endif /* _DEV_IC_HD64570VAR_H_ */
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