291 lines
9.8 KiB
Plaintext
291 lines
9.8 KiB
Plaintext
# $NetBSD: README.models,v 1.5 2016/06/19 10:49:34 rkujawa Exp $
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MIPS models and architecture levels
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-----------------------------------
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Since this is a complex and confusing topic and there's a shortage of
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information (especially, a shortage of reliable information), I'm
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creating this document as a reference for people doing MIPS stuff on
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NetBSD (and elsewhere).
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Citations appear in []. With luck all important facts have citations.
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------------------------------------------------------------
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1. Architecture levels.
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These architecture levels exist:
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32-bit 64-bit
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MIPS-I
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MIPS-II
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MIPS-III
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MIPS-IV
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MIPS-V
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MIPS32 MIPS64
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MIPS32r2 MIPS64r2
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MIPS32r3 MIPS64r3
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MIPS32r4 MIPS64r4
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MIPS32r5 MIPS64r5
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MIPS32r6 MIPS64r6
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Note that while MIPS32 is a 32-bit subset of MIPS64, each
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corresponding pair of MIPS32rN and MIPS64rN are comparable in age and
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properties. Later revisions (further down the list) are mostly supersets
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of earlier revisions, although some exceptions exist.
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------------------------------------------------------------
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2. CPU models.
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For vintage MIPS these are the standard models as of fall 1996 [idt96
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A-198] and the corresponding architecture levels. (There were many
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additional models put out by licensees or by the MIPS company itself,
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which have model numbers with fewer zeros.)
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R2000 MIPS-I (32-bit) [idt96 1-5]
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R3000 MIPS-I (32-bit) [idt96 1-5]
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R4000 MIPS-III (64-bit) [idt96 A-197]
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R4200 MIPS-III (64-bit) [idt96 A-197]
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R4300 MIPS-III (64-bit) [idt96 A-197]
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R4400 MIPS-III (64-bit) [idt96 A-197]
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R4600 MIPS-III (64-bit) [idt96 A-197]
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R5000 MIPS-IV (64-bit) [idt96 1-5]
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R6000 MIPS-II ??
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R8000 MIPS-IV (64-bit) [idt96 1-5]
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R10000 MIPS-IV (64-bit) [idt96 1-5]
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R1x000 MIPS-IV (64-bit)
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For later models than this I currently have no information.
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------------------------------------------------------------
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3. CPU models present in various systems.
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These are the CPU models found in various systems NetBSD does and
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doesn't support. This table also notes endianness; MIPS chips are
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bi-endian but are wired up one way or the other on motherboards.
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algor (little-endian [buildsh])
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Algorithmics P-4000i ??
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Algorithmics P-4032 ??
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Algorithmics P-5064 ??
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Algorithmics P-6032 ??
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arc (little-endian [buildsh])
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Acer PICA ??
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MIPS Magnum 4000 ??
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NEC Image RISCstation ??
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NEC Express RISCserver ??
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NEC RISCserver 2200 ??
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NEC RISCstation 2200 ??
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NEC RISCstation 2250 ??
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NEC Express5800/230 R4400 PCI presumably R4400 (MIPS-III)
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NEC Express5800/240 R4400 EISA presumably R4400 (MIPS-III)
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DeskStation Tyne ??
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cobalt (little-endian [buildsh])
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Qube ... ?? ??
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RaQ ... ?? ??
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emips (big-endian [buildsh])
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... ?? ??
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(see http://research.microsoft.com/en-us/projects/emips/ )
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evbmips
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Loongson 2F ( gdium, lemote etc. ) more or less LE MIPS-III with
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some extensions
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xburst ( as in, jz4780, found on CI20 ) LE MIPS32R2 with extensions
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... ?? ?? (various-endian)
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ews4800mips (big-endian [buildsh])
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EWS4800/350 ??
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EWS4800/350F ??
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EWS4800/360AD ??
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EWS4800/360ADII ??
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EWS4800/360SX ??
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EWS4800/360EX ??
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EWS4800/360 ??
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... ?? ??
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hpcmips (big-endian [buildsh])
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see http://wiki.netbsd.org/ports/hpcmips/processor_comparison/
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mipsco (big-endian [buildsh])
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Various MIPS Computer Systems, Inc. see [mipscolist]
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Bull DPX/Prostation M-20 ??
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newsmips (big-endian [buildsh])
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NWS-3470D R3000 (MIPS-I) [portpage]
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NWS-3410 R3000 (MIPS-I) [portpage]
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NWS-3460 R3000 (MIPS-I) [portpage]
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NWS-3710 R3000 (MIPS-I) [portpage]
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NWS-3720 R3000 (MIPS-I) [portpage]
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NWS-3800 series ??
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NWS-4000 series R4600 (MIPS-III) [portpage]
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NWS-5000 R4[04]00 (MIPS-III) [portpage]
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playstation2 (little-endian [buildsh])
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playstation2 R5900
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(almost all of MIPS-III + movn/movz) [linux-mips wiki R5900]
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pmax (little-endian [buildsh])
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DECstation/system 2100 and 3100 R2000 (MIPS-I) [portpage]
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DECsystem 5100 R3000 (MIPS-I) [portpage]
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Personal DECstation 5000/20, /25, /33 R3000 (MIPS-I) [portpage]
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Personal DECstation 5000/50 R4000 (MIPS-III) [portpage]
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DECstation/system 5000/120, /125, /133 R3000 (MIPS-I) [portpage]
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DECstation/system 5000/150 R4000 (MIPS-III) [portpage]
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DECstation/system 5000/200 R3000 (MIPS-I) [portpage]
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DECstation/system 5000/240 R3000 (MIPS-I) [portpage]
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DECstation/system 5000/260 R4400 (MIPS-III) [portpage]
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DECsystem 5900 R3000 (MIPS-I) [portpage]
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DECsystem 5900-260 R4400 (MIPS-III) [portpage]
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DECsystem 5500 R3000 (MIPS-I) [portpage]
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sbmips
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BCM91250A (Swarm) evaluation board Broadcomm BCM1250 [portpage]
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sgimips (big-endian [buildsh])
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4D/20 ??
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4D/25 ??
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Indigo R3000 (MIPS-I) [portpage]
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Indigo (R4x00) R4?00 (MIPS-III) [portpage]
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4D/30 ??
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4D/35 ??
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Indigo2 (R4x00) R4?00 (MIPS-III) [portpage]
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Challenge M ??
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Indy (R4x00) R4?00 (MIPS-III) [portpage]
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Indy (R5000) R5000 (MIPS-IV) [portpage]
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Challenge S (R4x00) R4?00 (MIPS-III) [portpage]
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Challenge S (R5000) R5000 (MIPS-IV) [portpage]
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R10000 Power Indigo2 R10000 (MIPS-IV) [portpage]
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Octane R1x000 (MIPS-IV) [portpage]
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O2 (R5000) R5000 (MIPS-IV) [portpage]
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O2 (RM5200) RM5200 (MIPS-IV) [portpage]
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O2 (R7000) R7000 (MIPS-IV) [portpage]
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O2 (R10000) R10000 (MIPS-IV) [portpage]
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O2 (R12000) R12000 (MIPS-IV) [portpage]
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O2 (R14000) R14000 (MIPS-IV) [portpage]
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Fuel R1x000 (MIPS-IV) [portpage]
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Tezro R1x000 (MIPS-IV) [portpage]
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... ??
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------------------------------------------------------------
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4. FPU properties
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TBD... this is complex and messy (XXX / ??)
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------------------------------------------------------------
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5. Exception handling properties
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TBD... (XXX / ??)
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------------------------------------------------------------
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6. MMU properties
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TBD... (XXX / ??)
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------------------------------------------------------------
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7. Cache properties
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TBD... (XXX / ??)
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------------------------------------------------------------
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8. Instruction ordering properties and hazards
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TBD... (XXX / ??)
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In the absence of the SYNC instruction before MIPS-II [idt96 A-172,
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mips32insn 215], apparently on a R3000 you can force pending memory
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writes to complete by doing an uncached read. [idt96 11-13]
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Apparently also on some models but not others the state of the write
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buffer is wired to the coprocessor 0 condition bit and you can also do
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this by using the otherwise useless bc0f instruction (branch on
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coprocessor 0 false) to loop. [no citation, I found this in passing
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the other day with Google while looking for something else]
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------------------------------------------------------------
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9. Pipeline hazards
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TBD... (XXX / ??)
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On MIPS-I a load instruction requires an explicit one-cycle wait
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before using the result. This restriction was lifted in MIPS-II,
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with the addition of an interlock in the pipeline. [idt96 A-2]
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A multiply should not be started within two cycles of a MFHI or MFLO
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instruction, as an interrupt that requires restarting the MFHI or MFLO
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might (will) get the result from the subsequent multiply. At least on
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MIPS-I. [idt96 2-4] I guess this is true for divides as well.
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------------------------------------------------------------
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10. Coprocessor 0 hazards
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TBD... (XXX / ??)
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----------------------------------------------------------------------
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11. Deprecated/removed material.
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When the exception handling model was changed for MIPS-III
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(introducing the ERET instruction) the RFE instruction supporting the
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old model was removed. [idt96 A-134]
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Coprocessor 3 (that is, the ability to have a third coprocessor, which
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had never been used for anything) was removed in MIPS-III [idt96 A-197].
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The branch likely instructions (e.g. BEQL) were added in MIPS-II
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[mips32insn 56] and deprecated not long after, at least by MIPS32
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[mips32insn 57] and were removed in release MIPS32 Release 6
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[mips32newinsn2a 71].
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SSNOP as a special NOP was deprecated in MIPS32/64 Release 6
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[mips32newinsn2a 375] and sequences using SSNOP should include the
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new EHB which counts as an SSNOP on older implementations
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[mips32newinsn2a 174] ... and possibly SYNC/SYNCI ???
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[mips32newinsn2a 394-401]
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... ??
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------------------------------------------------------------
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12. Conditional compilation in NetBSD
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TBD... (XXX / ??)
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------------------------------------------------------------
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References:
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[buildsh] The MACHINE/MACHINE_ARCH architecture table in NetBSD
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build.sh.
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[idt96] "IDT MIPS Microprocessor Family Software Reference Manual",
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Integrated Device Technology, Version 2.0, dated October 1996.
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[linux-mips wiki] https://www.linux-mips.org/wiki/
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[mips32intro] "MIPS32(TM) Architecture For Programmers Volume I:
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Introduction to the MIPS32(TM) Architecture", MIPS
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Technologies, Document Number MD00082, Revision 0.95, dated
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March 2001. This was apparently an external review version or
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something and has been available on the Internet; the final
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version, and later revisions, never were. (AFAIK)
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[mips32insn] "MIPS32(TM) Architecture For Programmers Volume II: The
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MIPS32(TM) Instruction Set", MIPS Technologies, Document Number
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MD00086, Revision 0.95, March 12, 2001. Ditto.
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[mips32newinsn2a] "MIPS32(R) Architecture For Programmers Volume II-A:
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The MIPS32(R) Instruction Set Manual", Imagination, Document
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Number MD00086, Revision 6.02, dated December 10, 2014.
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[mips32priv] "MIPS32(TM) Architecture For Programmers Volume III: The
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MIPS32(TM) Privileged Resource Architecture", Document Number
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MD00090, Revision 0.95, dated March 2001. Ditto.
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[portpage] The port page for this NetBSD port on wiki.netbsd.org, or a
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subpage. Ideally these references should be replaced with
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something less self-referential.
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[mipscolist] List of MIPS Computer Systems, Inc. machines hosted on the
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NetBSD web server: https://www.netbsd.org/ports/mipsco/models.html
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