182 lines
7.2 KiB
C
182 lines
7.2 KiB
C
/* $NetBSD: reg.h,v 1.1 2002/06/05 01:04:23 fredette Exp $ */
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/* $OpenBSD: reg.h,v 1.7 2000/06/15 17:00:37 mickey Exp $ */
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/*
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* Copyright (c) 1998 Michael Shalayeff
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Michael Shalayeff.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1990,1994 The University of Utah and
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* the Computer Systems Laboratory at the University of Utah (CSL).
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* All rights reserved.
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*
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* Permission to use, copy, modify and distribute this software is hereby
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* granted provided that (1) source code retains these copyright, permission,
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* and disclaimer notices, and (2) redistributions including binaries
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* reproduce the notices in supporting documentation, and (3) all advertising
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* materials mentioning features or use of this software display the following
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* acknowledgement: ``This product includes software developed by the
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* Computer Systems Laboratory at the University of Utah.''
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*
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* THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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* IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
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* ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* CSL requests users of this software to return to csl-dist@cs.utah.edu any
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* improvements that they make and grant CSL redistribution rights.
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*
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* Utah $Hdr: regs.h 1.6 94/12/14$
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* Author: Bob Wheeler, University of Utah CSL
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*/
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#ifndef _HPPA_REG_H_
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#define _HPPA_REG_H_
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/*
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* constants for registers for use with the following routines:
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*
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* void mtctl(reg, value) - move to control register
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* int mfctl(reg) - move from control register
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* int mtsp(sreg, value) - move to space register
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* int mfsr(sreg) - move from space register
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*/
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#define CR_RCTR 0
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#define CR_PIDR1 8
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#define CR_PIDR2 9
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#define CR_CCR 10
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#define CR_SAR 11
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#define CR_PIDR3 12
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#define CR_PIDR4 13
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#define CR_IVA 14
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#define CR_EIEM 15
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#define CR_ITMR 16
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#define CR_PCSQ 17
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#define CR_PCOQ 18
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#define CR_IIR 19
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#define CR_ISR 20
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#define CR_IOR 21
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#define CR_IPSW 22
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#define CR_EIRR 23
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#define CR_HPTMASK 24
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#define CR_VTOP 25
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#define CR_TR2 26
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#define CR_TR3 27
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#define CR_HVTP 28 /* points to a faulted HVT slot on LC cpus */
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#define CR_TR5 29
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#define CR_UPADDR 30 /* paddr of U-area of curproc */
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#define CR_TR7 31
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/*
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* Diagnostic registers and bit positions
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*/
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#define DR_CPUCFG 0
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#define DR0_PCXS_DHPMC 10 /* r/c D-cache error flag */
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#define DR0_PCXS_ILPMC 14 /* r/c I-cache error flag */
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#define DR0_PCXS_EQWSTO 16 /* r/w enable quad-word stores */
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#define DR0_PCXS_IHE 18 /* r/w I-cache sid hash enable */
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#define DR0_PCXS_DOMAIN 19
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#define DR0_PCXS_DHE 20 /* r/w D-cache sid hash enable */
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#define DR0_PCXT_DHPMC 10 /* r/c L1 D-cache error flag */
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#define DR0_PCXT_ILPMC 14 /* r/c L1 I-cache error flag */
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#define DR0_PCXT_IHE 18 /* r/w I-cache sid hash enable */
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#define DR0_PCXT_DHE 20 /* r/w D-cache sid hash enable */
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#define DR0_PCXL_L2IHPMC 6 /* r/c L2 I-cache error flag */
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#define DR0_PCXL_L2IHPMC_DIS 7 /* r/w L2 I-cache hpmc disable mask */
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#define DR0_PCXL_L2DHPMC 8 /* r/c L2 D-cache error flag */
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#define DR0_PCXL_L2DHPMC_DIS 9 /* r/w L2 D-cache hpmc disable mask */
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#define DR0_PCXL_L1IHPMC 10 /* r/c L1 I-cache error flag */
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#define DR0_PCXL_L1IHPMC_DIS 11 /* r/w L1 I-cache hpmc disable mask */
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#define DR0_PCXL_L2PARERR 15 /* r/c L2 Cache parity error (4 bit) */
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#define DR0_PCXL_STORE0 16 /* r/w scratch space */
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#define DR0_PCXL_PFMASK 17 /* r/w power-fail trap mask */
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#define DR0_PCXL_STORE1 18 /* r/w scratch */
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#define DR0_PCXL_FASTMODE 19 /* r 0-fast, 1-slow */
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#define DR0_PCXL_ISTRM_EN 20 /* r/w I-cache streaming enable */
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#define DR0_PCXL_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */
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#define DR0_PCXL_ENDIAN 23 /* r/w little endian traps */
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#define DR0_PCXL_SOU_EN 24 /* r/w stall-on-use on dc misses */
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#define DR0_PCXL_SHINT_EN 25 /* r/w no-fill on miss store hints */
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#define DR0_PCXL_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */
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#define DR0_PCXL_L2DHASH_EN 27 /* r/w L2 D-cache hash enable */
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#define DR0_PCXL_L2IHASH_EN 28 /* r/w L2 I-cache hash enable */
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#define DR0_PCXL_L1ICACHE_EN 29 /* r/w L1 I-cache enable */
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#define DR0_PCXL_HIT 30 /* r Diag cache read hit indication */
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#define DR0_PCXL_PARERR 31 /* r Diag cache read parity error */
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#define DR0_PCXL2_L1DHPMC 8 /* r/c L1 D-cache error flag */
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#define DR0_PCXL2_L1DHPMC_DIS 9 /* r/w L1 D-cache hpmc disable */
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#define DR0_PCXL2_L2DHPMC 10 /* r/c L1 I-cache error flag */
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#define DR0_PCXL2_L2DHPMC_DIS 11 /* r/w L1 I-cache hpmc disable */
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#define DR0_PCXL2_STORE0 16 /* r/w scratch space */
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#define DR0_PCXL2_PFMASK 17 /* r/w power-fail trap mask */
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#define DR0_PCXL2_STORE1 18 /* r/w scratch */
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#define DR0_PCXL2_DCSAFE 19 /* r/w serialize all data cache hangs */
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#define DR0_PCXL2_ISTRM_EN 20 /* r/w I-cache streaming enable */
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#define DR0_PCXL2_DUAL_DIS 22 /* r/w disable dual-issue (2 bit) */
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#define DR0_PCXL2_ENDIAN 23 /* r/w little endian traps */
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#define DR0_PCXL2_SOU_EN 24 /* r/w stall-on-use on dc misses */
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#define DR0_PCXL2_SHINT_EN 25 /* r/w no-fill on miss store hints */
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#define DR0_PCXL2_IPREF_EN 26 /* r/w L2 to L1 I-cache prefetch */
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#define DR0_PCXL2_LMIN_EN 27 /* r/w minor ill insn traps on LIH */
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#define DR0_PCXL2_RMIN_EN 28 /* r/w major ill insn traps on RIH */
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#define DR0_PCXL2_L1CACHE_EN 29 /* r/w L1 I-cache enable */
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#define DR_DTLB 8
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#define DR_ITLB 9
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#define DR_ITLB_SIZE_1 24
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#define DR_ITLB_SIZE_0 25
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#define DR_DTLB_SIZE_1 26
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#define DR_DTLB_SIZE_0 27
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#define CCR_MASK 0xff
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#define HPPA_NREGS (32)
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#define HPPA_NFPREGS (33) /* 33rd is used for r0 in fpemul */
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#ifndef _LOCORE
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struct reg {
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u_int32_t r_regs[HPPA_NREGS];
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/* p'bably some cr* ? */
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};
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struct fpreg {
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u_int64_t fpr_regs[HPPA_NFPREGS];
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};
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#endif /* !_LOCORE */
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#endif /* _HPPA_REG_H_ */
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