289 lines
7.7 KiB
C
289 lines
7.7 KiB
C
/* $NetBSD: tx39biu.c,v 1.5 2001/06/14 11:09:55 uch Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_tx39_debug.h"
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#include "opt_tx39_watchdogtimer.h"
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#include "opt_tx39biudebug.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/bus.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/tx/tx39biureg.h>
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#include <hpcmips/tx/txcsbusvar.h>
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#define ISSET(x, s) ((x) & (1 << (s)))
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#define ISSETPRINT(r, s, m) __is_set_print((u_int32_t)(r), \
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TX39_MEMCONFIG##s##_##m, #m)
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int tx39biu_match(struct device *, struct cfdata *, void *);
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void tx39biu_attach(struct device *, struct device *, void *);
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void tx39biu_callback(struct device *);
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int tx39biu_print(void *, const char *);
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int tx39biu_intr(void *);
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static void *__sc; /* XXX */
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void tx39biu_dump(tx_chipset_tag_t);
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struct tx39biu_softc {
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struct device sc_dev;
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tx_chipset_tag_t sc_tc;
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};
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struct cfattach tx39biu_ca = {
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sizeof(struct tx39biu_softc), tx39biu_match, tx39biu_attach
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};
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int
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tx39biu_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return (ATTACH_NORMAL);
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}
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void
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tx39biu_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct txsim_attach_args *ta = aux;
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struct tx39biu_softc *sc = (void*)self;
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tx_chipset_tag_t tc;
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#ifdef TX39_WATCHDOGTIMER
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txreg_t reg;
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#endif
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sc->sc_tc = tc = ta->ta_tc;
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printf("\n");
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#ifdef TX39BIUDEBUG
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tx39biu_dump(tc);
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#endif
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#ifdef TX39_WATCHDOGTIMER
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/*
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* CLRWRBUSERRINT Bus error connected CPU HwInt0
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*/
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reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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reg |= TX39_MEMCONFIG4_ENWATCH;
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reg = TX39_MEMCONFIG4_WATCHTIMEVAL_SET(reg, 0xf);
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tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
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reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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if (reg & TX39_MEMCONFIG4_ENWATCH) {
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int i;
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i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg);
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i = (1000 * (i + 1) * 64) / 36864;
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printf("WatchDogTimerRate: %dus\n", i);
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}
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#endif
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__sc = sc;
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/* Clear watch dog timer interrupt */
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tx39biu_intr(sc);
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/*
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* Chip select virtual bridge
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*/
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config_defer(self, tx39biu_callback);
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}
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void
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tx39biu_callback(self)
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struct device *self;
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{
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struct tx39biu_softc *sc = (void*)self;
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struct csbus_attach_args cba;
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cba.cba_busname = "txcsbus";
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cba.cba_tc = sc->sc_tc;
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config_found(self, &cba, tx39biu_print);
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}
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int
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tx39biu_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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return (pnp ? QUIET : UNCONF);
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}
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int
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tx39biu_intr(arg)
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void *arg;
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{
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struct tx39biu_softc *sc = __sc;
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tx_chipset_tag_t tc;
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txreg_t reg;
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if (!sc) {
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return (0);
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}
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tc = sc->sc_tc;
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/* Clear interrupt */
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reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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reg |= TX39_MEMCONFIG4_CLRWRBUSERRINT;
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tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
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reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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reg &= ~TX39_MEMCONFIG4_CLRWRBUSERRINT;
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tx_conf_write(tc, TX39_MEMCONFIG4_REG, reg);
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return (0);
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}
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void
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tx39biu_dump(tc)
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tx_chipset_tag_t tc;
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{
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char *rowsel[] = {"18,17:9", "22,18,20,19,17:9", "20,22,21,19,17:9",
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"22,23,21,19,17:9"};
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char *colsel[] = {"22,20,18,8:1", "19,18,8:2", "21,20,18,8:2",
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"23,22,20,18,8:2", "24,22,20,18,8:2",
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"18,p,X,8:0","22,p,X,21,8:0", "18,p,X,21,8:1",
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"22,p,X,23,21,8:1", "24,23,21,8:2"};
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txreg_t reg;
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int i;
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/*
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* Memory config 0 register
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*/
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reg = tx_conf_read(tc, TX39_MEMCONFIG0_REG);
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printf(" config0:");
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ISSETPRINT(reg, 0, ENDCLKOUTTRI);
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ISSETPRINT(reg, 0, DISDQMINIT);
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ISSETPRINT(reg, 0, ENSDRAMPD);
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ISSETPRINT(reg, 0, SHOWDINO);
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ISSETPRINT(reg, 0, ENRMAP2);
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ISSETPRINT(reg, 0, ENRMAP1);
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ISSETPRINT(reg, 0, ENWRINPAGE);
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ISSETPRINT(reg, 0, ENCS3USER);
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ISSETPRINT(reg, 0, ENCS2USER);
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ISSETPRINT(reg, 0, ENCS1USER);
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ISSETPRINT(reg, 0, ENCS1DRAM);
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ISSETPRINT(reg, 0, CS3SIZE);
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ISSETPRINT(reg, 0, CS2SIZE);
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ISSETPRINT(reg, 0, CS1SIZE);
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ISSETPRINT(reg, 0, CS0SIZE);
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printf("\n");
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for (i = 0; i < 2; i++) {
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int r, c;
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printf(" BANK%d: ", i);
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switch (i ? TX39_MEMCONFIG0_BANK1CONF(reg)
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: TX39_MEMCONFIG0_BANK0CONF(reg)) {
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case TX39_MEMCONFIG0_BANKCONF_16BITSDRAM:
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printf("16bit SDRAM");
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break;
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case TX39_MEMCONFIG0_BANKCONF_8BITSDRAM:
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printf("8bit SDRAM");
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break;
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case TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM:
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printf("32bit DRAM/HDRAM");
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break;
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case TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM:
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printf("16bit DRAM/HDRAM");
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break;
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}
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if (i == 1) {
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r = TX39_MEMCONFIG0_ROWSEL1(reg);
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c = TX39_MEMCONFIG0_COLSEL1(reg);
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} else {
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r = TX39_MEMCONFIG0_ROWSEL0(reg);
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c = TX39_MEMCONFIG0_COLSEL0(reg);
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}
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printf(" ROW %s COL %s\n", rowsel[r], colsel[c]);
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}
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/*
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* Memory config 3 register
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*/
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printf(" config3:");
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reg = tx_conf_read(tc, TX39_MEMCONFIG3_REG);
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#ifdef TX391X
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ISSETPRINT(reg, 3, ENMCS3PAGE);
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ISSETPRINT(reg, 3, ENMCS2PAGE);
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ISSETPRINT(reg, 3, ENMCS1PAGE);
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ISSETPRINT(reg, 3, ENMCS0PAGE);
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#endif /* TX391X */
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ISSETPRINT(reg, 3, ENCS3PAGE);
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ISSETPRINT(reg, 3, ENCS2PAGE);
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ISSETPRINT(reg, 3, ENCS1PAGE);
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ISSETPRINT(reg, 3, ENCS0PAGE);
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ISSETPRINT(reg, 3, CARD2WAITEN);
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ISSETPRINT(reg, 3, CARD1WAITEN);
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ISSETPRINT(reg, 3, CARD2IOEN);
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ISSETPRINT(reg, 3, CARD1IOEN);
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#ifdef TX391X
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ISSETPRINT(reg, 3, PORT8SEL);
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#endif /* TX391X */
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#ifdef TX392X
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ISSETPRINT(reg, 3, CARD2_8SEL);
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ISSETPRINT(reg, 3, CARD1_8SEL);
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#endif /* TX392X */
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printf("\n");
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/*
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* Memory config 4 register
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*/
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reg = tx_conf_read(tc, TX39_MEMCONFIG4_REG);
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printf(" config4:");
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ISSETPRINT(reg, 4, ENBANK1HDRAM);
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ISSETPRINT(reg, 4, ENBANK0HDRAM);
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ISSETPRINT(reg, 4, ENARB);
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ISSETPRINT(reg, 4, DISSNOOP);
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ISSETPRINT(reg, 4, CLRWRBUSERRINT);
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ISSETPRINT(reg, 4, ENBANK1OPT);
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ISSETPRINT(reg, 4, ENBANK0OPT);
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ISSETPRINT(reg, 4, ENWATCH);
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ISSETPRINT(reg, 4, MEMPOWERDOWN);
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ISSETPRINT(reg, 4, ENRFSH1);
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ISSETPRINT(reg, 4, ENRFSH0);
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if (reg & TX39_MEMCONFIG4_ENWATCH) {
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i = TX39_MEMCONFIG4_WATCHTIMEVAL(reg);
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i = (1000 * (i + 1) * 64) / 36864;
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printf("WatchDogTimerRate: %dus", i);
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}
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printf("\n");
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}
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