7a599d2c3e
The Massbus disk drivers should be merged with the vax Massbus disk drivers when the 4.4BSD Massbus code gets free.
136 lines
5.8 KiB
C
136 lines
5.8 KiB
C
/* $NetBSD: rhreg.h,v 1.1 2003/08/19 10:51:57 ragge Exp $ */
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/*
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* Copyright (c) 2003 Anders Magnusson (ragge@ludd.luth.se).
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* RH20 register definitions.
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*/
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/*
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* Different device codes.
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*/
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#define RH_DT_RP04 0x10
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#define RH_DT_RP05 0x11
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#define RH_DT_RP06 0x12
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#define RH_DT_RP07 0x22
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#define RH_DT_RM02 0x15
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#define RH_DT_RM03 0x14
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#define RH_DT_RM05 0x17
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#define RH_DT_RM80 0x16
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#define RH_DT_TU45 052
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#define RH_DT_DRQ 0x800 /* Dual ported */
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#define RH_DT_MOH 0x2000 /* Moving head device */
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/*
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* Some common registers used in the rh device driver.
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*/
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#define RH_DS 1 /* unit status */
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#define RH_AS 4 /* attention summary */
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#define RH_DT 6 /* drive type */
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#define RH_SBAR 070 /* Bus address register */
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#define RH_STCR 071 /* Transfer control register */
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#define RH_IVIR 074 /* Interrupt vector register */
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#define RH_DS_DPR 0x100 /* Unit present */
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/*
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* Internal register bits.
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*/
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#define RH_BAR_ADRMSK 0177777 /* Disk/tape address mask */
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#define RH_TCR_RCLP 0002000000000 /* Reset channel when starting */
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#define RH_TCR_SES 0000200000000 /* Store status after transfer */
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#define RH_TCR_DTES 0000000200000 /* Don't stop if errors */
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#define RH_TCR_NBC 0000000177700 /* Negative block count */
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#define RH_TCR_NBCSH 6 /* Block count shift */
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/*
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* RH20 register definitions.
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*/
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#define RH20_CONI_BPE 0400000 /* Data bus parity error */
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#define RH20_CONI_EXC 0200000 /* Exception */
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#define RH20_CONI_LWE 0100000 /* Long word count error */
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#define RH20_CONI_SWE 0040000 /* Short word count error */
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#define RH20_CONI_MBE 0020000 /* MBOX error */
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#define RH20_CONI_DRE 0010000 /* Drive response error */
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#define RH20_CONI_RAE 0004000 /* Register access error */
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#define RH20_CONI_MBH 0002000 /* MBOX halted */
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#define RH20_CONI_OVR 0001000 /* Data overrun */
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#define RH20_CONI_MEN 0000400 /* Massbus enable */
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#define RH20_CONI_ATN 0000200 /* Drive attention */
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#define RH20_CONI_2RF 0000100 /* Secondary command register full */
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#define RH20_CONI_ATE 0000040 /* Attention enable */
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#define RH20_CONI_1RF 0000020 /* Primary command register full */
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#define RH20_CONI_DON 0000010 /* Channel done */
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#define RH20_CONO_RAE 0004000 /* Clear RAE */
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#define RH20_CONO_RST 0002000 /* Controller reset */
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#define RH20_CONO_XFR 0001000 /* Clear transfer error */
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#define RH20_CONO_MEN 0000400 /* Massbus enable */
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#define RH20_CONO_RCL 0000200 /* Reset MBOX command list pointer */
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#define RH20_CONO_DEL 0000100 /* Delete secondary command */
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#define RH20_CONO_ATE 0000040 /* Enable attention interrupts */
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#define RH20_CONO_STP 0000020 /* Stop current command */
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#define RH20_CONO_DON 0000010 /* Clear done */
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#define RH20_CONO_IMSK 0000007 /* Mask for interrupt level */
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#define RH20_DATAI_CBPE 0001000000000 /* Control bus parity error */
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#define RH20_DATAI_TRA 0000200000000 /* Transfer received */
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#define RH20_DATAI_CPA 0000000200000 /* Massbus parity bit */
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#define RH20_DATAO_RS 0770000000000 /* Register select */
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#define RH20_DATAO_LR 0004000000000 /* Load register */
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#define RH20_DATAO_RAES 0000400000000 /* RAE Suppress */
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/*
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* Data channel defines.
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*/
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#define DCH_CCL_OFF 0 /* Channel Command List opcode */
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#define DCH_CST_OFF 1 /* Channel Status Word */
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#define DCH_CCW_OFF 2 /* Current Channel Command Word */
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#define DCH_CIV_OFF 3 /* Unused, free for software to use */
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#define DCH_CCW_HLT 0000000000000 /* HALT opcode */
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#define DCH_CCW_JMP 0200000000000 /* JUMP opcode */
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#define DCH_CCW_XFR 0400000000000 /* XFER opcode, plus next 2 bits: */
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#define DCH_CCW_XHLT 0200000000000 /* Xfer cmd: "Halt after xfer" */
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#define DCH_CCW_XREV 0100000000000 /* Xfer cmd: "Reverse xfer" */
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#define DCH_CCW_CNTMSK 0077760000000 /* Word Count (positive) */
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#define DCH_CCW_CNTSH 22 /* Word Count shift */
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#define DCH_CCW_ADRMSK 0000017777777 /* 22-bit address */
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/* Channel Status Word
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*/
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#define DCH_CSW_SET 0400000000000 /* Always set 1 */
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#define DCH_CSW_MPAR 0200000000000 /* Mem Par Err during CCW fetch */
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#define DCH_CSW_NOAPE 0100000000000 /* Set if NO mem addr par err */
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#define DCH_CSW_NOWC0 0040000000000 /* CCW count NOT 0 when CSW set */
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#define DCH_CSW_NXM 0020000000000 /* Chan referenced NXM */
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#define DCH_CSW_LXFE 0000400000000 /* Last Transfer Error */
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#define DCH_CSW_RH20E 0000200000000 /* RH20 tried to start not-ready chn */
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#define DCH_CSW_LWCE 0000100000000 /* Long Word Count Error */
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#define DCH_CSW_SWCE 0000040000000 /* Short Word Count Error */
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#define DCH_CSW_OVN 0000020000000 /* Overrun */
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#define DCH_CSW_ADRMSK 0000017777777 /* 22-bit CCW addr+1 */
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