75 lines
2.6 KiB
C
75 lines
2.6 KiB
C
/* $NetBSD: pciide.c,v 1.9 2015/07/11 10:32:45 kamil Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <lib/libsa/stand.h>
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#include <mips/cpuregs.h>
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#include "boot.h"
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#include "wdvar.h"
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#define COBALT_IO_SPACE_BASE 0x10000000 /* XXX VT82C586 ISA I/O space */
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int
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pciide_init(struct wdc_channel *chp, u_int *unit)
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{
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uint32_t cmdreg, ctlreg;
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int i, compatchan = 0;
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/*
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* two channels per chip, two drives per channel
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*/
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compatchan = *unit / PCIIDE_CHANNEL_NDEV;
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if (compatchan >= PCIIDE_NUM_CHANNELS)
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return (ENXIO);
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*unit %= PCIIDE_CHANNEL_NDEV;
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DPRINTF(("[pciide] unit: %d, channel: %d\n", *unit, compatchan));
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/*
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* XXX map?
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*/
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cmdreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
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PCIIDE_COMPAT_CMD_BASE(compatchan));
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ctlreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
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PCIIDE_COMPAT_CTL_BASE(compatchan));
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/* set up cmd registers */
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chp->c_cmdbase = (uint8_t *)cmdreg;
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chp->c_data = (uint16_t *)(cmdreg + wd_data);
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for (i = 0; i < WDC_NPORTS; i++)
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chp->c_cmdreg[i] = chp->c_cmdbase + i;
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/* set up shadow registers */
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chp->c_cmdreg[wd_status] = chp->c_cmdreg[wd_command];
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chp->c_cmdreg[wd_features] = chp->c_cmdreg[wd_precomp];
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/* set up ctl registers */
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chp->c_ctlbase = (uint8_t *)ctlreg;
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return 0;
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}
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