164 lines
5.8 KiB
C
164 lines
5.8 KiB
C
/* $NetBSD: ncr5380var.h,v 1.1 1995/10/29 21:19:10 gwr Exp $ */
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/*
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* Copyright (c) 1995 David Jones, Gordon W. Ross
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* Copyright (c) 1994 Jarle Greipsland
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* David Jones and Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* This file defines the interface between the machine-dependent
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* module and the machine-indepenedent ncr5380sbc.c module.
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*/
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#define SCI_CLR_INTR(sc) (*(sc)->sci_iack)
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#define SCI_BUSY(sc) (*sc->sci_bus_csr & SCI_BUS_BSY)
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#define PHASE_DATA_OUT 0x0
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#define PHASE_DATA_IN 0x1
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#define PHASE_CMD 0x2
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#define PHASE_STATUS 0x3
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#define PHASE_UNSPEC1 0x4
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#define PHASE_UNSPEC2 0x5
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#define PHASE_MSG_OUT 0x6
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#define PHASE_MSG_IN 0x7
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#define PHASE_INVALID -1
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#define SCSI_PHASE(x) ((x)&0x7)
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/* Per-request state. This is required in order to support reselection. */
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struct sci_req {
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struct scsi_xfer *sr_xs; /* Pointer to xfer struct, NULL=unused */
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int sr_target, sr_lun; /* For fast access */
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void *sr_dma_hand; /* Current DMA hnadle */
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u_char *sr_data; /* Saved data pointer */
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int sr_datalen;
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int sr_flags; /* Internal error code */
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#define SR_IMMED 1 /* Immediate command */
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#define SR_SENSE 2 /* We are getting sense */
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#define SR_ERROR 4 /* Error occurred */
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int sr_status; /* Status code from last cmd */
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};
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#define SCI_OPENINGS 4 /* Up to 4 commands at once */
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struct ncr5380_softc {
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struct device sc_dev;
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struct scsi_link sc_link;
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/* Pointers to 5380 registers. MD code must set these up. */
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volatile u_char *sci_data;
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volatile u_char *sci_icmd;
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volatile u_char *sci_mode;
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volatile u_char *sci_tcmd;
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volatile u_char *sci_bus_csr;
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volatile u_char *sci_csr;
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volatile u_char *sci_idata;
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volatile u_char *sci_iack;
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/* Functions set from MD code */
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int (*sc_pio_out) __P((struct ncr5380_softc *,
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int, int, u_char *));
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int (*sc_pio_in) __P((struct ncr5380_softc *,
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int, int, u_char *));
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void (*sc_dma_alloc) __P((struct ncr5380_softc *));
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void (*sc_dma_free) __P((struct ncr5380_softc *));
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void (*sc_dma_start) __P((struct ncr5380_softc *));
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void (*sc_dma_poll) __P((struct ncr5380_softc *));
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void (*sc_dma_eop) __P((struct ncr5380_softc *));
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void (*sc_dma_stop) __P((struct ncr5380_softc *));
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int sc_flags; /* Misc. flags and capabilities */
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#define NCR5380_PERMIT_RESELECT 1 /* Allow disconnect/reselect */
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int sc_min_dma_len; /* Smaller than this is done with PIO */
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/* Begin MI shared data */
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/* Active data pointer for current SCSI process */
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u_char *sc_dataptr;
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int sc_datalen;
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void *sc_dma_hand; /* DMA handle */
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u_int sc_dma_flags;
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#define DMA5380_INPROGRESS 1 /* MD: DMA is curently in progress */
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#define DMA5380_WRITE 2 /* MI: DMA is to output to SCSI */
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#define DMA5380_POLL 4 /* MI: Poll for DMA completion */
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#define DMA5380_ERROR 8 /* MD: DMA operation failed */
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#define DMA5380_PHYS 16 /* MI: Buffer has B_PHYS set */
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/* Begin MI private data */
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/* The request that has the bus now. */
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struct sci_req *sc_current;
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/* The number of operations in progress on the bus */
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volatile int sc_ncmds;
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/* Ring buffer of pending/active requests */
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struct sci_req sc_ring[SCI_OPENINGS];
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int sc_rr; /* Round-robin scan pointer */
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/* Active requests, by target/LUN */
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struct sci_req *sc_matrix[8][8];
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/* Message stuff */
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int sc_prevphase;
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int sc_msg_flags;
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#define NCR_DROP_MSGIN 1
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#define NCR_ABORTING 2
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#define NCR_NEED_RESET 4
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u_int sc_msgpriq; /* Messages we want to send */
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u_int sc_msgoutq; /* Messages sent during last MESSAGE OUT */
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u_int sc_msgout; /* Message last transmitted */
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#define SEND_DEV_RESET 0x01
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#define SEND_PARITY_ERROR 0x02
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#define SEND_ABORT 0x04
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#define SEND_REJECT 0x08
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#define SEND_INIT_DET_ERR 0x10
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#define SEND_IDENTIFY 0x20
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#define SEND_SDTR 0x40
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#define SEND_WDTR 0x80
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#define NCR_MAX_MSG_LEN 8
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u_char sc_omess[NCR_MAX_MSG_LEN];
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u_char *sc_omp; /* Outgoing message pointer */
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u_char sc_imess[NCR_MAX_MSG_LEN];
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u_char *sc_imp; /* Incoming message pointer */
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};
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void ncr5380_init __P((struct ncr5380_softc *));
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void ncr5380_reset_scsibus __P((struct ncr5380_softc *));
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int ncr5380_sbc_intr __P((struct ncr5380_softc *));
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int ncr5380_scsi_cmd __P((struct scsi_xfer *));
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int ncr5380_pio_in __P((struct ncr5380_softc *, int, int, u_char *));
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int ncr5380_pio_out __P((struct ncr5380_softc *, int, int, u_char *));
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