138 lines
5.0 KiB
C
138 lines
5.0 KiB
C
/* $NetBSD: ncr5380reg.h,v 1.1 1995/10/29 21:19:08 gwr Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* HISTORY (mach3)
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* Revision 2.3 91/08/24 12:25:10 af
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* Moved padding of regmap in impl file.
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* [91/08/02 04:22:39 af]
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*
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* Revision 2.2 91/06/19 16:28:35 rvb
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* From the NCR data sheets
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* "NCR 5380 Family, SCSI Protocol Controller Data Manual"
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* NCR Microelectronics Division, Colorado Spring, 6/98 T01891L
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* [91/04/21 af]
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*
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*/
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/*
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* File: scsi_5380.h
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* Author: Alessandro Forin, Carnegie Mellon University
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* Date: 5/91
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*
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* Defines for the NCR 5380 (SCSI chip), aka Am5380
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*/
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/*
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* Register map
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*/
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typedef struct {
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volatile unsigned char sci_data; /* r: Current data */
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#define sci_odata sci_data /* w: Out data */
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volatile unsigned char sci_icmd; /* rw: Initiator command */
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volatile unsigned char sci_mode; /* rw: Mode */
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volatile unsigned char sci_tcmd; /* rw: Target command */
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volatile unsigned char sci_bus_csr; /* r: Bus Status */
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#define sci_sel_enb sci_bus_csr /* w: Select enable */
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volatile unsigned char sci_csr; /* r: Status */
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#define sci_dma_send sci_csr /* w: Start dma send data */
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volatile unsigned char sci_idata; /* r: Input data */
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#define sci_trecv sci_idata /* w: Start dma receive, target */
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volatile unsigned char sci_iack; /* r: Interrupt Acknowledge */
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#define sci_irecv sci_iack /* w: Start dma receive, initiator */
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} sci_regmap_t;
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/*
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* Initiator command register
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*/
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#define SCI_ICMD_DATA 0x01 /* rw: Assert data bus */
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#define SCI_ICMD_ATN 0x02 /* rw: Assert ATN signal */
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#define SCI_ICMD_SEL 0x04 /* rw: Assert SEL signal */
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#define SCI_ICMD_BSY 0x08 /* rw: Assert BSY signal */
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#define SCI_ICMD_ACK 0x10 /* rw: Assert ACK signal */
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#define SCI_ICMD_LST 0x20 /* r: Lost arbitration */
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#define SCI_ICMD_DIFF SCI_ICMD_LST /* w: Differential cable */
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#define SCI_ICMD_AIP 0x40 /* r: Arbitration in progress */
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#define SCI_ICMD_TEST SCI_ICMD_AIP /* w: Test mode */
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#define SCI_ICMD_RST 0x80 /* rw: Assert RST signal */
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/* Bits to keep when doing read/modify/write (leave out RST) */
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#define SCI_ICMD_RMASK 0x1F
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/*
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* Mode register
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*/
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#define SCI_MODE_ARB 0x01 /* rw: Start arbitration */
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#define SCI_MODE_DMA 0x02 /* rw: Enable DMA xfers */
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#define SCI_MODE_MONBSY 0x04 /* rw: Monitor BSY signal */
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#define SCI_MODE_DMA_IE 0x08 /* rw: Enable DMA complete interrupt */
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#define SCI_MODE_PERR_IE 0x10 /* rw: Interrupt on parity errors */
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#define SCI_MODE_PAR_CHK 0x20 /* rw: Check parity */
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#define SCI_MODE_TARGET 0x40 /* rw: Target mode (Initiator if 0) */
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#define SCI_MODE_BLOCKDMA 0x80 /* rw: Block-mode DMA handshake (MBZ) */
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/*
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* Target command register
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*/
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#define SCI_TCMD_IO 0x01 /* rw: Assert I/O signal */
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#define SCI_TCMD_CD 0x02 /* rw: Assert C/D signal */
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#define SCI_TCMD_MSG 0x04 /* rw: Assert MSG signal */
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#define SCI_TCMD_PHASE_MASK 0x07 /* r: Mask for current bus phase */
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#define SCI_TCMD_REQ 0x08 /* rw: Assert REQ signal */
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#define SCI_TCMD_LAST_SENT 0x80 /* ro: Last byte was xferred
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* (not on 5380/1) */
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#define SCI_PHASE(x) ((x)&0x7)
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/*
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* Current (SCSI) Bus status (.sci_bus_csr)
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*/
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#define SCI_BUS_DBP 0x01 /* r: Data Bus parity */
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#define SCI_BUS_SEL 0x02 /* r: SEL signal */
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#define SCI_BUS_IO 0x04 /* r: I/O signal */
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#define SCI_BUS_CD 0x08 /* r: C/D signal */
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#define SCI_BUS_MSG 0x10 /* r: MSG signal */
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#define SCI_BUS_REQ 0x20 /* r: REQ signal */
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#define SCI_BUS_BSY 0x40 /* r: BSY signal */
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#define SCI_BUS_RST 0x80 /* r: RST signal */
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#define SCI_CUR_PHASE(x) SCI_PHASE((x)>>2)
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/*
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* Bus and Status register (.sci_csr)
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*/
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#define SCI_CSR_ACK 0x01 /* r: ACK signal */
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#define SCI_CSR_ATN 0x02 /* r: ATN signal */
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#define SCI_CSR_DISC 0x04 /* r: Disconnected (BSY==0) */
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#define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
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#define SCI_CSR_INT 0x10 /* r: Interrupt request */
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#define SCI_CSR_PERR 0x20 /* r: Parity error */
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#define SCI_CSR_DREQ 0x40 /* r: DMA request */
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#define SCI_CSR_DONE 0x80 /* r: DMA count is zero */
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