212 lines
7.0 KiB
C
212 lines
7.0 KiB
C
/* $NetBSD: locore.h,v 1.12 1997/06/22 04:30:01 jonathan Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Jump table for MIPS cpu locore functions that are implemented
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* differently on different generations, or instruction-level
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* archtecture (ISA) level, the Mips family.
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* The following functions must be provided for each mips ISA level:
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*
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*
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* MachConfigCache
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* MachFlushCache
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* MachFlushDCache
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* MachFlushICache
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* MachForceCacheUpdate
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* MachSetPID
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* MachTLBFlush
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* MachTLBFlushAddr __P()
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* MachTLBUpdate (u_int, (pt_entry_t?) u_int);
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* wbflush
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* proc_trampoline()
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* switch_exit()
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* cpu_switch_resume()
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*
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* We currently provide support for:
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*
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* r2000 and r3000 (mips ISA-I)
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* r4000 and r4400 in 32-bit mode (mips ISA-III?)
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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/*
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* locore service routine for exeception vectors. Used outside locore
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* only to print them by name in stack tracebacks
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*/
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extern void mips1_ConfigCache __P((void));
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extern void mips1_FlushCache __P((void));
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extern void mips1_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips1_ForceCacheUpdate __P((void));
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extern void mips1_SetPID __P((int pid));
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extern void mips1_TLBFlush __P((void));
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extern void mips1_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern int mips1_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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extern void mips1_TLBWriteIndexed __P((u_int index, u_int high,
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u_int low));
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extern void mips1_wbflush __P((void));
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extern void mips1_proc_trampoline __P((void));
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extern void mips1_switch_exit __P((struct proc *));
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extern void mips1_cpu_switch_resume __P((void));
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extern void mips3_ConfigCache __P((void));
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extern void mips3_FlushCache __P((void));
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extern void mips3_FlushDCache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips3_FlushICache __P((vm_offset_t addr, vm_offset_t len));
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extern void mips3_ForceCacheUpdate __P((void));
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extern void mips3_HitFlushDCache __P((vm_offset_t, int));
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extern void mips3_SetPID __P((int pid));
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extern void mips3_TLBFlush __P((void));
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extern void mips3_TLBFlushAddr __P( /* XXX Really pte highpart ? */
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(vm_offset_t addr));
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extern int mips3_TLBUpdate __P((u_int, /*pt_entry_t*/ u_int));
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extern void mips3_TLBWriteIndexedVPS __P((u_int index, void *tlb));
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extern void mips3_TLBWriteIndexed __P((u_int index, u_int high,
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u_int lo0, u_int lo1));
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extern void mips3_wbflush __P((void));
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extern void mips3_proc_trampoline __P((void));
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extern void mips3_switch_exit __P((struct proc *));
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extern void mips3_cpu_switch_resume __P((void));
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extern void mips3_SetWIRED __P((int));
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/*
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* A vector with an entry for each mips-ISA-level dependent
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* locore function, and macros which jump through it.
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* XXX the macro names are chosen to be compatible with the old
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* Sprite coding-convention names used in 4.4bsd/pmax.
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*/
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typedef struct {
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void (*configCache) __P((void));
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void (*flushCache) __P((void));
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void (*flushDCache) __P((vm_offset_t addr, vm_offset_t len));
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void (*flushICache) __P((vm_offset_t addr, vm_offset_t len));
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void (*forceCacheUpdate) __P((void));
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void (*setTLBpid) __P((int pid));
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void (*tlbFlush) __P((void));
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void (*tlbFlushAddr) __P((vm_offset_t)); /* XXX Really pte highpart ? */
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int (*tlbUpdate) __P((u_int highreg, u_int lowreg));
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void (*wbflush) __P((void));
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void (*proc_trampoline) __P((void));
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void (*mips_switch_exit) __P((struct proc *));
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void (*cpu_switch_resume) __P((void));
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} mips_locore_jumpvec_t;
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/*
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* The "active" locore-fuction vector, and
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*/
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extern mips_locore_jumpvec_t mips_locore_jumpvec;
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extern mips_locore_jumpvec_t r2000_locore_vec;
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extern mips_locore_jumpvec_t r4000_locore_vec;
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#if defined(MIPS3) && !defined (MIPS1)
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#define MachConfigCache mips3_ConfigCache
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#define MachFlushCache mips3_FlushCache
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#define MachFlushDCache mips3_FlushDCache
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#define MachFlushICache mips3_FlushICache
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#define MachForceCacheUpdate mips3_ForceCacheUpdate
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#define MachSetPID mips3_SetPID
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#define MachTLBFlush mips3_TLBFlush
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#define MachTLBFlushAddr mips3_TLBFlushAddr
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#define MachTLBUpdate mips3_TLBUpdate
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#define wbflush mips3_wbflush
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#define proc_trampoline mips3_proc_trampoline
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#define switch_exit mips3_switch_exit
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#endif
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#if !defined(MIPS3) && defined (MIPS1)
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#define MachConfigCache mips1_ConfigCache
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#define MachFlushCache mips1_FlushCache
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#define MachFlushDCache mips1_FlushDCache
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#define MachFlushICache mips1_FlushICache
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#define MachForceCacheUpdate mips1_ForceCacheUpdate
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#define MachSetPID mips1_SetPID
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#define MachTLBFlush mips1_TLBFlush
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#define MachTLBFlushAddr mips1_TLBFlushAddr
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#define MachTLBUpdate mips1_TLBUpdate
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#define wbflush mips1_wbflush
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#define proc_trampoline mips1_proc_trampoline
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#define switch_exit mips1_switch_exit
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#endif
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#if defined(MIPS3) && defined (MIPS1)
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#define MachConfigCache (*(mips_locore_jumpvec.configCache))
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#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
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#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
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#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
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#define MachForceCacheUpdate (*(mips_locore_jumpvec.forceCacheUpdate))
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MachTLBFlush (*(mips_locore_jumpvec.tlbFlush))
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#define MachTLBFlushAddr (*(mips_locore_jumpvec.tlbFlushAddr))
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#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
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#define wbflush (*(mips_locore_jumpvec.wbflush))
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#define proc_trampoline (mips_locore_jumpvec.proc_trampoline)
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#define switch_exit (*(mips_locore_jumpvec.mips_switch_exit))
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#endif
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/* cpu_switch_resume not called directly */
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/*
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* CPU identification, from PRID register.
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*/
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union cpuprid {
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int cpuprid;
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struct {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int pad1:16; /* reserved */
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u_int cp_imp:8; /* implementation identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_minrev:4; /* minor revision identifier */
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#else
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u_int cp_minrev:4; /* minor revision identifier */
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u_int cp_majrev:4; /* major revision identifier */
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u_int cp_imp:8; /* implementation identifier */
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u_int pad1:16; /* reserved */
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#endif
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} cpu;
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};
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#ifdef _KERNEL
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/*
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* Global variables used to communicate CPU type, and parameters
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* such as cache size, from locore to higher-level code (e.g., pmap).
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*/
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extern union cpuprid cpu_id;
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extern union cpuprid fpu_id;
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extern int cpu_arch;
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extern u_int mips_L1DataCacheSize;
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extern u_int mips_L1InstCacheSize;
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extern u_int mips_L1DataCacheLSize;
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extern u_int mips_L1InstCacheLSize;
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extern u_int mips_L2CacheSize;
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extern u_int mips_L2CacheLSize;
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extern u_int mips_CacheAliasMask;
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extern struct intr_tab intr_tab[];
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#endif
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#endif /* _MIPS_LOCORE_H */
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