138 lines
4.5 KiB
C
138 lines
4.5 KiB
C
/* $NetBSD: intr.h,v 1.4 1999/07/03 08:22:53 dbj Exp $ */
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/*
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* Copyright (C) 1997 Scott Reynolds
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* Copyright (C) 1998 Darrin Jewell
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NEXT68K_INTR_H_
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#define _NEXT68K_INTR_H_
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#include <machine/psl.h>
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/* Probably want to dealwith IPL's here @@@ */
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#ifdef _KERNEL
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/*
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* spl functions; all but spl0 are done in-line
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*/
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#define _spl(s) \
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({ \
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register int _spl_r; \
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\
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__asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" : \
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"&=d" (_spl_r) : "di" (s)); \
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_spl_r; \
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})
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#define _splraise(s) \
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({ \
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int _spl_r; \
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\
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__asm __volatile (" \
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clrl d0 ; \
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movw sr,d0 ; \
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movl d0,%0 ; \
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andw #0x700,d0 ; \
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movw %1,d1 ; \
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andw #0x700,d1 ; \
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cmpw d0,d1 ; \
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jle 1f ; \
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movw %1,sr ; \
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1:" : \
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"&=d" (_spl_r) : \
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"di" (s) : \
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"d0", "d1"); \
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_spl_r; \
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})
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/* spl0 requires checking for software interrupts */
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#define spl1() _spl(PSL_S|PSL_IPL1)
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#define spl2() _spl(PSL_S|PSL_IPL2)
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#define spl3() _spl(PSL_S|PSL_IPL3)
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#define spl4() _spl(PSL_S|PSL_IPL4)
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#define spl5() _spl(PSL_S|PSL_IPL5)
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#define spl6() _spl(PSL_S|PSL_IPL6)
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#define spl7() _spl(PSL_S|PSL_IPL7)
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/* watch out for side effects */
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#define splx(s) ((s) & PSL_IPL ? _spl(s) : spl0())
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/****************************************************************/
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#define splhigh() spl7()
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#define splserial() _splraise(PSL_S|PSL_IPL5)
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#define splsched() _splraise(PSL_S|PSL_IPL3)
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#define splclock() _splraise(PSL_S|PSL_IPL6)
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#define splstatclock() splclock()
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#define splimp() _splraise(PSL_S|PSL_IPL6)
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#define spltty() _splraise(PSL_S|PSL_IPL3)
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#define splbio() _splraise(PSL_S|PSL_IPL3)
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#define splnet() _splraise(PSL_S|PSL_IPL3)
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#define splsoftnet() _splraise(PSL_S|PSL_IPL2)
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#define splsoftclock() spl1()
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#define spldma() _splraise(PSL_S|PSL_IPL6)
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/****************************************************************/
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/*
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* simulated software interrupt register
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*/
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extern volatile u_int8_t ssir;
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#define SIR_NET 0x01
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#define SIR_CLOCK 0x02
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#define SIR_SERIAL 0x04
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#define SIR_DTMGR 0x08
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#define SIR_ADB 0x10
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#define siron(mask) \
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__asm __volatile ( "orb %1,%0" : "=m" (ssir) : "i" (mask))
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#define siroff(mask) \
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__asm __volatile ( "andb %1,%0" : "=m" (ssir) : "ir" (~(mask)));
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#define setsoftnet() siron(SIR_NET)
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#define setsoftclock() siron(SIR_CLOCK)
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#define setsoftserial() siron(SIR_SERIAL)
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#define setsoftdtmgr() siron(SIR_DTMGR)
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#define setsoftadb() siron(SIR_ADB)
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extern u_long allocate_sir __P((void (*)(void),void *));
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extern void init_sir __P((void));
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/* locore.s */
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int spl0 __P((void));
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#endif /* _KERNEL */
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#define INTR_SETMASK(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))=(x))
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#define INTR_ENABLE(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))|=NEXT_I_BIT(x))
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#define INTR_DISABLE(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRMASK))&=(~NEXT_I_BIT(x)))
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#define INTR_OCCURRED(x) ((*(volatile u_long *)IIOV(NEXT_P_INTRSTAT))& NEXT_I_BIT(x))
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#endif /* _NEXT68K_INTR_H_ */
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