72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/* $NetBSD: ciareg.h,v 1.6 1996/11/13 21:13:27 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* 21171 Chipset registers and constants.
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*
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* Taken from XXX
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*/
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#define REGVAL(r) (*(int32_t *)ALPHA_PHYS_TO_K0SEG(r))
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/*
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* Base addresses
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*/
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#define CIA_PCI_SMEM1 0x8000000000UL
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#define CIA_PCI_SMEM2 0x8400000000UL
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#define CIA_PCI_SMEM3 0x8500000000UL
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#define CIA_PCI_SIO1 0x8580000000UL
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#define CIA_PCI_SIO2 0x85c0000000UL
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#define CIA_PCI_DENSE 0x8600000000UL
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#define CIA_PCI_CONF 0x8700000000UL
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#define CIA_PCI_IACK 0x8720000000UL
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#define CIA_CSRS 0x8740000000UL
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#define CIA_PCI_MC_CSRS 0x8750000000UL
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#define CIA_PCI_ATRANS 0x8760000000UL
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/*
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* General CSRs
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*/
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#define CIA_CSR_HAE_MEM (CIA_CSRS + 0x400)
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#define HAE_MEM_REG1_START(x) (((u_int32_t)(x) & 0xe0000000UL) << 0)
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#define HAE_MEM_REG1_MASK 0x1fffffffUL
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#define HAE_MEM_REG2_START(x) (((u_int32_t)(x) & 0x0000f800UL) << 16)
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#define HAE_MEM_REG2_MASK 0x07ffffffUL
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#define HAE_MEM_REG3_START(x) (((u_int32_t)(x) & 0x000000fcUL) << 16)
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#define HAE_MEM_REG3_MASK 0x03ffffffUL
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#define CIA_CSR_HAE_IO (CIA_CSRS + 0x440)
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#define HAE_IO_REG1_START(x) 0UL
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#define HAE_IO_REG1_MASK 0x01ffffffUL
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#define HAE_IO_REG2_START(x) (((u_int32_t)(x) & 0xfe000000UL) << 0)
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#define HAE_IO_REG2_MASK 0x01ffffffUL
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