664 lines
20 KiB
C
664 lines
20 KiB
C
/* $NetBSD: aic7xxx_inline.h,v 1.9 2006/02/16 20:17:16 perry Exp $ */
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/*
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* Inline routines shareable across OS platforms.
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*
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* Copyright (c) 1994-2001 Justin T. Gibbs.
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* Copyright (c) 2000-2001 Adaptec Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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* //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#39 $
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*
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* $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.20 2003/01/20 20:44:55 gibbs Exp $
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*/
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/*
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* Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
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*/
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#ifndef _AIC7XXX_INLINE_H_
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#define _AIC7XXX_INLINE_H_
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/************************* Sequencer Execution Control ************************/
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static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
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static __inline int ahc_is_paused(struct ahc_softc *ahc);
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static __inline void ahc_pause(struct ahc_softc *ahc);
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static __inline void ahc_unpause(struct ahc_softc *ahc);
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/*
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* Work around any chip bugs related to halting sequencer execution.
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* On Ultra2 controllers, we must clear the CIOBUS stretch signal by
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* reading a register that will set this signal and deassert it.
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* Without this workaround, if the chip is paused, by an interrupt or
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* manual pause while accessing scb ram, accesses to certain registers
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* will hang the system (infinite pci retries).
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*/
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static __inline void
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ahc_pause_bug_fix(struct ahc_softc *ahc)
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{
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if ((ahc->features & AHC_ULTRA2) != 0)
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(void)ahc_inb(ahc, CCSCBCTL);
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}
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/*
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* Determine whether the sequencer has halted code execution.
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* Returns non-zero status if the sequencer is stopped.
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*/
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static __inline int
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ahc_is_paused(struct ahc_softc *ahc)
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{
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return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
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}
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/*
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* Request that the sequencer stop and wait, indefinitely, for it
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* to stop. The sequencer will only acknowledge that it is paused
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* once it has reached an instruction boundary and PAUSEDIS is
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* cleared in the SEQCTL register. The sequencer may use PAUSEDIS
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* for critical sections.
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*/
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static __inline void
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ahc_pause(struct ahc_softc *ahc)
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{
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ahc_outb(ahc, HCNTRL, ahc->pause);
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/*
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* Since the sequencer can disable pausing in a critical section, we
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* must loop until it actually stops.
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*/
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while (ahc_is_paused(ahc) == 0)
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;
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ahc_pause_bug_fix(ahc);
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}
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/*
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* Allow the sequencer to continue program execution.
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* We check here to ensure that no additional interrupt
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* sources that would cause the sequencer to halt have been
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* asserted. If, for example, a SCSI bus reset is detected
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* while we are fielding a different, pausing, interrupt type,
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* we don't want to release the sequencer before going back
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* into our interrupt handler and dealing with this new
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* condition.
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*/
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static __inline void
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ahc_unpause(struct ahc_softc *ahc)
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{
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if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
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ahc_outb(ahc, HCNTRL, ahc->unpause);
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}
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/*********************** Untagged Transaction Routines ************************/
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static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
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static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
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/*
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* Block our completion routine from starting the next untagged
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* transaction for this target or target lun.
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*/
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static __inline void
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ahc_freeze_untagged_queues(struct ahc_softc *ahc)
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{
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if ((ahc->flags & AHC_SCB_BTT) == 0)
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ahc->untagged_queue_lock++;
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}
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/*
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* Allow the next untagged transaction for this target or target lun
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* to be executed. We use a counting semaphore to allow the lock
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* to be acquired recursively. Once the count drops to zero, the
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* transaction queues will be run.
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*/
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static __inline void
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ahc_release_untagged_queues(struct ahc_softc *ahc)
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{
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if ((ahc->flags & AHC_SCB_BTT) == 0) {
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ahc->untagged_queue_lock--;
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if (ahc->untagged_queue_lock == 0)
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ahc_run_untagged_queues(ahc);
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}
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}
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/************************** Memory mapping routines ***************************/
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static __inline struct ahc_dma_seg *
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ahc_sg_bus_to_virt(struct scb *scb,
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uint32_t sg_busaddr);
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static __inline uint32_t
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ahc_sg_virt_to_bus(struct scb *scb,
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struct ahc_dma_seg *sg);
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static __inline uint32_t
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ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
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static __inline void ahc_sync_scb(struct ahc_softc *ahc,
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struct scb *scb, int op);
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static __inline void ahc_sync_sglist(struct ahc_softc *ahc,
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struct scb *scb, int op);
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static __inline uint32_t
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ahc_targetcmd_offset(struct ahc_softc *ahc,
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u_int index);
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static __inline struct ahc_dma_seg *
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ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
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{
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int sg_index;
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sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
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/* sg_list_phys points to entry 1, not 0 */
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sg_index++;
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return (&scb->sg_list[sg_index]);
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}
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static __inline uint32_t
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ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
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{
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int sg_index;
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/* sg_list_phys points to entry 1, not 0 */
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sg_index = sg - &scb->sg_list[1];
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return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
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}
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static __inline uint32_t
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ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
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{
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return (ahc->scb_data->hscb_busaddr
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+ (sizeof(struct hardware_scb) * index));
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}
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static __inline void
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ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
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{
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ahc_dmamap_sync(ahc, ahc->parent_dmat,
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ahc->scb_data->hscb_dmamap,
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/*offset*/(scb->hscb - ahc->scb_data->hscbs) * sizeof(*scb->hscb),
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/*len*/sizeof(*scb->hscb), op);
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}
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static __inline void
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ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
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{
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if (scb->sg_count == 0)
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return;
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ahc_dmamap_sync(ahc, ahc->parent_dmat, scb->sg_map->sg_dmamap,
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/*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
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* sizeof(struct ahc_dma_seg),
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/*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
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}
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static __inline uint32_t
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ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
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{
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return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
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}
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/******************************** Debugging ***********************************/
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static __inline char *ahc_name(struct ahc_softc *ahc);
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static __inline char *
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ahc_name(struct ahc_softc *ahc)
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{
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return (ahc->name);
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}
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/*********************** Miscellaneous Support Functions ***********************/
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static __inline void ahc_update_residual(struct ahc_softc *ahc,
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struct scb *scb);
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static __inline struct ahc_initiator_tinfo *
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ahc_fetch_transinfo(struct ahc_softc *ahc,
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char channel, u_int our_id,
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u_int remote_id,
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struct ahc_tmode_tstate **tstate);
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static __inline uint16_t
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ahc_inw(struct ahc_softc *ahc, u_int port);
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static __inline void ahc_outw(struct ahc_softc *ahc, u_int port,
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u_int value);
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static __inline uint32_t
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ahc_inl(struct ahc_softc *ahc, u_int port);
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static __inline void ahc_outl(struct ahc_softc *ahc, u_int port,
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uint32_t value);
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static __inline uint64_t
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ahc_inq(struct ahc_softc *ahc, u_int port);
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static __inline void ahc_outq(struct ahc_softc *ahc, u_int port,
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uint64_t value);
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static __inline struct scb*
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ahc_get_scb(struct ahc_softc *ahc);
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static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
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static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc,
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struct scb *scb);
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static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
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static __inline struct scsi_sense_data *
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ahc_get_sense_buf(struct ahc_softc *ahc,
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struct scb *scb);
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static __inline uint32_t
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ahc_get_sense_bufaddr(struct ahc_softc *ahc,
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struct scb *scb);
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/*
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* Determine whether the sequencer reported a residual
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* for this SCB/transaction.
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*/
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static __inline void
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ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
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{
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uint32_t sgptr;
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sgptr = ahc_le32toh(scb->hscb->sgptr);
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if ((sgptr & SG_RESID_VALID) != 0)
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ahc_calc_residual(ahc, scb);
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}
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/*
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* Return pointers to the transfer negotiation information
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* for the specified our_id/remote_id pair.
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*/
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static __inline struct ahc_initiator_tinfo *
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ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
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u_int remote_id, struct ahc_tmode_tstate **tstate)
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{
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/*
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* Transfer data structures are stored from the perspective
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* of the target role. Since the parameters for a connection
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* in the initiator role to a given target are the same as
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* when the roles are reversed, we pretend we are the target.
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*/
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/*if (channel == 'B')
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our_id += 8;*/
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*tstate = ahc->enabled_targets[our_id];
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return (&(*tstate)->transinfo[remote_id]);
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}
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static __inline uint16_t
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ahc_inw(struct ahc_softc *ahc, u_int port)
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{
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return ((ahc_inb(ahc, port+1) << 8) | ahc_inb(ahc, port));
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}
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static __inline void
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ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
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{
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ahc_outb(ahc, port, value & 0xFF);
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ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
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}
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static __inline uint32_t
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ahc_inl(struct ahc_softc *ahc, u_int port)
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{
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return ((ahc_inb(ahc, port))
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| (ahc_inb(ahc, port+1) << 8)
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| (ahc_inb(ahc, port+2) << 16)
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| (ahc_inb(ahc, port+3) << 24));
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}
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static __inline void
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ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
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{
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ahc_outb(ahc, port, (value) & 0xFF);
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ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
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ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
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ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
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}
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static __inline uint64_t
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ahc_inq(struct ahc_softc *ahc, u_int port)
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{
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return ((ahc_inb(ahc, port))
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| (ahc_inb(ahc, port+1) << 8)
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| (ahc_inb(ahc, port+2) << 16)
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| (ahc_inb(ahc, port+3) << 24)
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| (((uint64_t)ahc_inb(ahc, port+4)) << 32)
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| (((uint64_t)ahc_inb(ahc, port+5)) << 40)
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| (((uint64_t)ahc_inb(ahc, port+6)) << 48)
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| (((uint64_t)ahc_inb(ahc, port+7)) << 56));
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}
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static __inline void
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ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
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{
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ahc_outb(ahc, port, value & 0xFF);
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ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
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ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
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ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
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ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
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ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
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ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
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ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
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}
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/*
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* Get a free scb. If there are none, see if we can allocate a new SCB.
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*/
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static __inline struct scb *
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ahc_get_scb(struct ahc_softc *ahc)
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{
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struct scb *scb;
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if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL)
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return (NULL);
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SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
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return (scb);
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}
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/*
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* Return an SCB resource to the free list.
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*/
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static __inline void
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ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
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{
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struct hardware_scb *hscb;
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hscb = scb->hscb;
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/* Clean up for the next user */
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ahc->scb_data->scbindex[hscb->tag] = NULL;
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scb->flags = SCB_FREE;
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hscb->control = 0;
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SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
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/* Notify the OSM that a resource is now available. */
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ahc_platform_scb_free(ahc, scb);
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}
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static __inline struct scb *
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ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
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{
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struct scb* scb;
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scb = ahc->scb_data->scbindex[tag];
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if (scb != NULL)
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ahc_sync_scb(ahc, scb,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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return (scb);
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}
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static __inline void
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ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
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{
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struct hardware_scb *q_hscb;
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u_int saved_tag;
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/*
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* Our queuing method is a bit tricky. The card
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* knows in advance which HSCB to download, and we
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* can't disappoint it. To achieve this, the next
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* SCB to download is saved off in ahc->next_queued_scb.
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* When we are called to queue "an arbitrary scb",
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* we copy the contents of the incoming HSCB to the one
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* the sequencer knows about, swap HSCB pointers and
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* finally assign the SCB to the tag indexed location
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* in the scb_array. This makes sure that we can still
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* locate the correct SCB by SCB_TAG.
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*/
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q_hscb = ahc->next_queued_scb->hscb;
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saved_tag = q_hscb->tag;
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memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
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if ((scb->flags & SCB_CDB32_PTR) != 0) {
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q_hscb->shared_data.cdb_ptr =
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ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
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+ offsetof(struct hardware_scb, cdb32));
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}
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q_hscb->tag = saved_tag;
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q_hscb->next = scb->hscb->tag;
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/* Now swap HSCB pointers. */
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ahc->next_queued_scb->hscb = scb->hscb;
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scb->hscb = q_hscb;
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/* Now define the mapping from tag to SCB in the scbindex */
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ahc->scb_data->scbindex[scb->hscb->tag] = scb;
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}
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/*
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* Tell the sequencer about a new transaction to execute.
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*/
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static __inline void
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ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
|
|
{
|
|
ahc_swap_with_next_hscb(ahc, scb);
|
|
|
|
if (scb->hscb->tag == SCB_LIST_NULL
|
|
|| scb->hscb->next == SCB_LIST_NULL)
|
|
panic("Attempt to queue invalid SCB tag %x:%x\n",
|
|
scb->hscb->tag, scb->hscb->next);
|
|
/*
|
|
* Keep a history of SCBs we've downloaded in the qinfifo.
|
|
*/
|
|
ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
|
|
|
|
/*
|
|
* Make sure our data is consistent from the
|
|
* perspective of the adapter.
|
|
*/
|
|
ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
|
|
|
/* Tell the adapter about the newly queued SCB */
|
|
if ((ahc->features & AHC_QUEUE_REGS) != 0) {
|
|
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
|
|
} else {
|
|
if ((ahc->features & AHC_AUTOPAUSE) == 0)
|
|
ahc_pause(ahc);
|
|
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
|
|
if ((ahc->features & AHC_AUTOPAUSE) == 0)
|
|
ahc_unpause(ahc);
|
|
}
|
|
}
|
|
|
|
static __inline struct scsi_sense_data *
|
|
ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
|
|
{
|
|
int offset;
|
|
|
|
offset = scb - ahc->scb_data->scbarray;
|
|
return (&ahc->scb_data->sense[offset]);
|
|
}
|
|
|
|
static __inline uint32_t
|
|
ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
|
|
{
|
|
int offset;
|
|
|
|
offset = scb - ahc->scb_data->scbarray;
|
|
return (ahc->scb_data->sense_busaddr
|
|
+ (offset * sizeof(struct scsi_sense_data)));
|
|
}
|
|
|
|
/************************** Interrupt Processing ******************************/
|
|
static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op);
|
|
static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
|
|
static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
|
|
static __inline int ahc_intr(void *arg);
|
|
static __inline void ahc_minphys(struct buf *bp);
|
|
|
|
static __inline void
|
|
ahc_minphys(bp)
|
|
struct buf *bp;
|
|
{
|
|
/*
|
|
* Even though the card can transfer up to 16megs per command
|
|
* we are limited by the number of segments in the DMA segment
|
|
* list that we can hold. The worst case is that all pages are
|
|
* discontinuous physically, hence the "page per segment" limit
|
|
* enforced here.
|
|
*/
|
|
if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) {
|
|
bp->b_bcount = AHC_MAXTRANSFER_SIZE;
|
|
}
|
|
minphys(bp);
|
|
}
|
|
|
|
static __inline void
|
|
ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
|
|
{
|
|
ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
|
|
/*offset*/0, /*len*/256, op);
|
|
}
|
|
|
|
static __inline void
|
|
ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
|
|
{
|
|
#ifdef AHC_TARGET_MODE
|
|
if ((ahc->flags & AHC_TARGETROLE) != 0) {
|
|
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
|
|
ahc->shared_data_dmamap,
|
|
ahc_targetcmd_offset(ahc, 0),
|
|
sizeof(struct target_cmd) * AHC_TMODE_CMDS,
|
|
op);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* See if the firmware has posted any completed commands
|
|
* into our in-core command complete fifos.
|
|
*/
|
|
#define AHC_RUN_QOUTFIFO 0x1
|
|
#define AHC_RUN_TQINFIFO 0x2
|
|
static __inline u_int
|
|
ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
|
|
{
|
|
u_int retval;
|
|
|
|
retval = 0;
|
|
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, ahc->shared_data_dmamap,
|
|
/*offset*/ahc->qoutfifonext, /*len*/1,
|
|
BUS_DMASYNC_POSTREAD);
|
|
if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
|
|
retval |= AHC_RUN_QOUTFIFO;
|
|
#ifdef AHC_TARGET_MODE
|
|
if ((ahc->flags & AHC_TARGETROLE) != 0
|
|
&& (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
|
|
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
|
|
ahc->shared_data_dmamap,
|
|
ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
|
|
/*len*/sizeof(struct target_cmd),
|
|
BUS_DMASYNC_POSTREAD);
|
|
if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
|
|
retval |= AHC_RUN_TQINFIFO;
|
|
}
|
|
#endif
|
|
return (retval);
|
|
}
|
|
|
|
/*
|
|
* Catch an interrupt from the adapter
|
|
*/
|
|
static __inline int
|
|
ahc_intr(void *arg)
|
|
{
|
|
struct ahc_softc *ahc = (struct ahc_softc*)arg;
|
|
u_int intstat;
|
|
|
|
if ((ahc->pause & INTEN) == 0) {
|
|
/*
|
|
* Our interrupt is not enabled on the chip
|
|
* and may be disabled for re-entrancy reasons,
|
|
* so just return. This is likely just a shared
|
|
* interrupt.
|
|
*/
|
|
return 1;
|
|
}
|
|
/*
|
|
* Instead of directly reading the interrupt status register,
|
|
* infer the cause of the interrupt by checking our in-core
|
|
* completion queues. This avoids a costly PCI bus read in
|
|
* most cases.
|
|
*/
|
|
if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
|
|
&& (ahc_check_cmdcmpltqueues(ahc) != 0))
|
|
intstat = CMDCMPLT;
|
|
else {
|
|
intstat = ahc_inb(ahc, INTSTAT);
|
|
}
|
|
|
|
if (intstat & CMDCMPLT) {
|
|
ahc_outb(ahc, CLRINT, CLRCMDINT);
|
|
/*
|
|
* Ensure that the chip sees that we've cleared
|
|
* this interrupt before we walk the output fifo.
|
|
* Otherwise, we may, due to posted bus writes,
|
|
* clear the interrupt after we finish the scan,
|
|
* and after the sequencer has added new entries
|
|
* and asserted the interrupt again.
|
|
*/
|
|
ahc_flush_device_writes(ahc);
|
|
scsipi_channel_freeze(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
|
|
ahc_run_qoutfifo(ahc);
|
|
scsipi_channel_thaw(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
|
|
#ifdef AHC_TARGET_MODE
|
|
if ((ahc->flags & AHC_TARGETROLE) != 0)
|
|
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
|
|
#endif
|
|
}
|
|
|
|
if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
|
|
/* Hot eject */
|
|
return 1;
|
|
|
|
if ((intstat & INT_PEND) == 0) {
|
|
#if AHC_PCI_CONFIG > 0
|
|
if (ahc->unsolicited_ints > 500) {
|
|
ahc->unsolicited_ints = 0;
|
|
if ((ahc->chip & AHC_PCI) != 0
|
|
&& (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
|
|
ahc->bus_intr(ahc);
|
|
}
|
|
#endif
|
|
ahc->unsolicited_ints++;
|
|
return 1;
|
|
}
|
|
ahc->unsolicited_ints = 0;
|
|
|
|
if (intstat & BRKADRINT) {
|
|
ahc_handle_brkadrint(ahc);
|
|
/* Fatal error, no more interrupts to handle. */
|
|
return 1;
|
|
}
|
|
|
|
if ((intstat & (SEQINT|SCSIINT)) != 0)
|
|
ahc_pause_bug_fix(ahc);
|
|
|
|
if ((intstat & SEQINT) != 0)
|
|
ahc_handle_seqint(ahc, intstat);
|
|
|
|
if ((intstat & SCSIINT) != 0)
|
|
ahc_handle_scsiint(ahc, intstat);
|
|
|
|
return 1;
|
|
}
|
|
|
|
#endif /* _AIC7XXX_INLINE_H_ */
|