133 lines
4.5 KiB
C
133 lines
4.5 KiB
C
/* $NetBSD: ims332reg.h,v 1.2 2005/02/27 00:27:01 perry Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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* Defines for the Inmos IMS-G332 Colour video controller
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* Author: Alessandro Forin, Carnegie Mellon University
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* See: IMS G332 Colour Video Controller, 1990 Databook, pg 139-163,
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* Inmos, Ltd.
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*/
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/*
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* Although the chip is built to be memory-mapped
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* it can be programmed for 32 or 64 bit addressing.
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* Moreover, the hardware bits have been twisted
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* even more on the machine I am writing this for.
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* So I'll just define the chip's offsets and leave
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* it to the implementation to define the rest.
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*/
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#define IMS332_REG_BOOT 0x000 /* boot time config */
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#define IMS332_REG_HALF_SYNCH 0x021 /* datapath registers */
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#define IMS332_REG_BACK_PORCH 0x022
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#define IMS332_REG_DISPLAY 0x023
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#define IMS332_REG_SHORT_DIS 0x024
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#define IMS332_REG_BROAD_PULSE 0x025
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#define IMS332_REG_V_SYNC 0x026
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#define IMS332_REG_V_PRE_EQUALIZE 0x027
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#define IMS332_REG_V_POST_EQUALIZE 0x028
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#define IMS332_REG_V_BLANK 0x029
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#define IMS332_REG_V_DISPLAY 0x02a
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#define IMS332_REG_LINE_TIME 0x02b
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#define IMS332_REG_LINE_START 0x02c
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#define IMS332_REG_MEM_INIT 0x02d
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#define IMS332_REG_XFER_DELAY 0x02e
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#define IMS332_REG_COLOR_MASK 0x040 /* color mask register */
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#define IMS332_REG_CSR_A 0x060
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#define IMS332_REG_CSR_B 0x070
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#define IMS332_REG_TOP_SCREEN 0x080 /* top-of-screen offset */
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#define IMS332_REG_CURSOR_LUT_0 0x0a1 /* cursor palette */
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#define IMS332_REG_CURSOR_LUT_1 0x0a2
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#define IMS332_REG_CURSOR_LUT_2 0x0a3
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#define IMS332_REG_RGB_CKSUM_0 0x0c0 /* test registers */
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#define IMS332_REG_RGB_CKSUM_1 0x0c1
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#define IMS332_REG_RGB_CKSUM_2 0x0c2
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#define IMS332_REG_CURSOR_LOC 0x0c7 /* cursor location */
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#define IMS332_REG_LUT_BASE 0x100 /* color palette */
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#define IMS332_REG_LUT_END 0x1ff
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#define IMS332_REG_CURSOR_RAM 0x200 /* cursor bitmap */
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#define IMS332_REG_CURSOR_RAM_END 0x3ff
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/*
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* Control register A
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*/
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#define IMS332_CSR_A_VTG_ENABLE 0x000001 /* vertical timing generator */
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#define IMS332_CSR_A_INTERLACED 0x000002 /* screen format */
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#define IMS332_CSR_A_CCIR 0x000004 /* default is EIA */
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#define IMS332_CSR_A_SLAVE_SYNC 0x000008 /* else from our pll */
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#define IMS332_CSR_A_PLAIN_SYNC 0x000010 /* else tesselated */
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#define IMS332_CSR_A_SEPARATE_SYNC 0x000020 /* else composite */
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#define IMS332_CSR_A_VIDEO_ONLY 0x000040 /* else video+sync */
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#define IMS332_CSR_A_BLANK_PEDESTAL 0x000080 /* blank level */
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#define IMS332_CSR_A_CBLANK_IS_OUT 0x000100
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#define IMS332_CSR_A_CBLANK_NO_DELAY 0x000200
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#define IMS332_CSR_A_FORCE_BLANK 0x000400
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#define IMS332_CSR_A_BLANK_DISABLE 0x000800
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#define IMS332_CSR_A_VRAM_INCREMENT 0x003000
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# define IMS332_VRAM_INC_1 0x000000
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# define IMS332_VRAM_INC_256 0x001000 /* except interlaced->2 */
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# define IMS332_VRAM_INC_512 0x002000
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# define IMS332_VRAM_INC_1024 0x003000
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#define IMS332_CSR_A_DMA_DISABLE 0x004000
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#define IMS332_CSR_A_SYNC_DELAY_MASK 0x038000 /* 0-7 VTG clk delays */
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#define IMS332_CSR_A_PIXEL_INTERLEAVE 0x040000
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#define IMS332_CSR_A_DELAYED_SAMPLING 0x080000
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#define IMS332_CSR_A_BITS_PER_PIXEL 0x700000
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# define IMS332_BPP_1 0x000000
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# define IMS332_BPP_2 0x100000
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# define IMS332_BPP_4 0x200000
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# define IMS332_BPP_8 0x300000
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# define IMS332_BPP_15 0x400000
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# define IMS332_BPP_16 0x500000
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#define IMS332_CSR_A_DISABLE_CURSOR 0x800000
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/*
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* Control register B is mbz
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*/
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/*
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* Boot register
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*/
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#define IMS332_BOOT_PLL 0x00001f /* xPLL, binary */
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#define IMS332_BOOT_CLOCK_PLL 0x000020 /* else xternal */
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#define IMS332_BOOT_64_BIT_MODE 0x000040 /* else 32 */
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#define IMS332_BOOT_xxx 0xffff80 /* reserved, mbz */
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