290 lines
11 KiB
C
290 lines
11 KiB
C
/* $NetBSD: dptreg.h,v 1.16 2005/02/27 00:27:01 perry Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Andrew Doran <ad@NetBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IC_DPTREG_H_
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#define _IC_DPTREG_H_ 1
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/* Hardware limits */
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#define DPT_MAX_TARGETS 16
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#define DPT_MAX_LUNS 8
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#define DPT_MAX_CHANNELS 3
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/*
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* HBA registers
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*/
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#define HA_DATA 0
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#define HA_ERROR 1
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#define HA_DMA_BASE 2
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#define HA_ICMD_CODE2 4
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#define HA_ICMD_CODE1 5
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#define HA_ICMD 6
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/* EATA commands. There are many more that we don't define or use. */
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#define HA_COMMAND 7
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#define CP_PIO_GETCFG 0xf0 /* Read configuration data, PIO */
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#define CP_PIO_CMD 0xf2 /* Execute command, PIO */
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#define CP_DMA_GETCFG 0xfd /* Read configuration data, DMA */
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#define CP_DMA_CMD 0xff /* Execute command, DMA */
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#define CP_PIO_TRUNCATE 0xf4 /* Truncate transfer command, PIO */
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#define CP_RESET 0xf9 /* Reset controller and SCSI bus */
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#define CP_REBOOT 0x06 /* Reboot controller (last resort) */
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#define CP_IMMEDIATE 0xfa /* EATA immediate command */
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#define CPI_GEN_ABORT 0x00 /* Generic abort */
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#define CPI_SPEC_RESET 0x01 /* Specific reset */
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#define CPI_BUS_RESET 0x02 /* Bus reset */
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#define CPI_SPEC_ABORT 0x03 /* Specific abort */
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#define CPI_QUIET_INTR 0x04 /* ?? */
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#define CPI_ROM_DL_EN 0x05 /* ?? */
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#define CPI_COLD_BOOT 0x06 /* Cold boot HBA */
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#define CPI_FORCE_IO 0x07 /* ?? */
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#define CPI_BUS_OFFLINE 0x08 /* Set SCSI bus offline */
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#define CPI_RESET_MSKD_BUS 0x09 /* Reset masked bus */
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#define CPI_POWEROFF_WARN 0x0a /* Power about to fail */
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#define HA_STATUS 7
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#define HA_ST_ERROR 0x01
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#define HA_ST_MORE 0x02
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#define HA_ST_CORRECTD 0x04
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#define HA_ST_DRQ 0x08
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#define HA_ST_SEEK_COMPLETE 0x10
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#define HA_ST_WRT_FLT 0x20
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#define HA_ST_READY 0x40
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#define HA_ST_BUSY 0x80
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#define HA_ST_DATA_RDY (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ)
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#define HA_AUX_STATUS 8
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#define HA_AUX_BUSY 0x01
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#define HA_AUX_INTR 0x02
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/*
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* Structure of an EATA command packet.
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*/
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struct eata_cp {
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u_int8_t cp_ctl0; /* Control flags 0 */
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u_int8_t cp_senselen; /* Request sense length */
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u_int8_t cp_unused0[3]; /* Unused */
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u_int8_t cp_ctl1; /* Control flags 1 */
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u_int8_t cp_ctl2; /* Control flags 2 */
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u_int8_t cp_ctl3; /* Control flags 3 */
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u_int8_t cp_ctl4; /* Control flags 4 */
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u_int8_t cp_msg[3]; /* Message bytes 0-3 */
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u_int8_t cp_cdb_cmd; /* SCSI CDB */
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u_int8_t cp_cdb_more0[3]; /* SCSI CDB */
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u_int8_t cp_cdb_len; /* SCSI CDB */
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u_int8_t cp_cdb_more1[7]; /* SCSI CDB */
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u_int32_t cp_datalen; /* Bytes of data/SG list */
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u_int32_t cp_ccbid; /* ID of software CCB */
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u_int32_t cp_dataaddr; /* Addr of data/SG list */
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u_int32_t cp_stataddr; /* Addr of status packet */
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u_int32_t cp_senseaddr; /* Addr of req. sense */
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} __attribute__ ((__packed__));
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struct eata_ucp {
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u_int8_t ucp_cp[sizeof(struct eata_cp) - 5*4]; /* XXX */
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u_long ucp_datalen;
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u_long ucp_ccbid;
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caddr_t ucp_dataaddr;
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caddr_t ucp_stataddr;
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caddr_t ucp_senseaddr;
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u_long ucp_timeout;
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u_int8_t ucp_hstatus;
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u_int8_t ucp_tstatus;
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u_int8_t ucp_retries;
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u_int8_t ucp_padding;
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} __attribute__ ((__packed__));
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#define CP_C0_SCSI_RESET 0x01 /* Cause a bus reset */
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#define CP_C0_HBA_INIT 0x02 /* Reinitialize HBA */
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#define CP_C0_AUTO_SENSE 0x04 /* Auto request sense on error */
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#define CP_C0_SCATTER 0x08 /* Do scatter/gather I/O */
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#define CP_C0_QUICK 0x10 /* Return no status packet */
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#define CP_C0_INTERPRET 0x20 /* HBA interprets SCSI CDB */
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#define CP_C0_DATA_OUT 0x40 /* Data out phase */
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#define CP_C0_DATA_IN 0x80 /* Data in phase */
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#define CP_C1_TO_PHYS 0x01 /* Send to RAID component */
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#define CP_C1_RESERVED 0xfe
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#define CP_C2_PHYS_UNIT 0x01 /* Physical unit on mirrored pair */
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#define CP_C2_NO_AT 0x02 /* No address translation */
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#define CP_C2_NO_CACHE 0x04 /* No HBA caching */
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#define CP_C2_RESERVED 0xf8
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#define CP_C3_ID_MASK 0x1f /* Target ID */
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#define CP_C3_ID_SHIFT 0
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#define CP_C3_CHANNEL_MASK 0xe0 /* Target channel */
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#define CP_C3_CHANNEL_SHIFT 5
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#define CP_C4_LUN_MASK 0x07 /* Target LUN */
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#define CP_C4_LUN_SHIFT 0
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#define CP_C4_RESERVED 0x18
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#define CP_C4_LUN_TAR 0x20 /* CP is for target ROUTINE */
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#define CP_C4_DIS_PRI 0x40 /* Give disconnect privilege */
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#define CP_C4_IDENTIFY 0x80 /* Always true */
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/*
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* EATA status packet as returned by controller upon command completion. It
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* contains status, message info and a handle on the initiating CCB.
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*/
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struct eata_sp {
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u_int8_t sp_hba_status; /* Host adapter status */
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u_int8_t sp_scsi_status; /* SCSI bus status */
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u_int8_t sp_reserved[2]; /* Reserved */
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u_int32_t sp_inv_residue; /* Bytes not transferred */
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u_int32_t sp_ccbid; /* ID of software CCB */
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u_int8_t sp_id_message;
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u_int8_t sp_que_message;
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u_int8_t sp_tag_message;
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u_int8_t sp_messages[9];
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} __attribute__ ((__packed__));
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/*
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* HBA status as returned by status packet. Bit 7 signals end of command.
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*/
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#define SP_HBA_NO_ERROR 0x00 /* No error on command */
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#define SP_HBA_ERROR_SEL_TO 0x01 /* Device selection timeout */
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#define SP_HBA_ERROR_CMD_TO 0x02 /* Device command timeout */
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#define SP_HBA_ERROR_RESET 0x03 /* SCSI bus was reset */
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#define SP_HBA_INIT_POWERUP 0x04 /* Initial controller power up */
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#define SP_HBA_UNX_BUSPHASE 0x05 /* Unexpected bus phase */
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#define SP_HBA_UNX_BUS_FREE 0x06 /* Unexpected bus free */
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#define SP_HBA_BUS_PARITY 0x07 /* SCSI bus parity error */
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#define SP_HBA_SCSI_HUNG 0x08 /* SCSI bus hung */
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#define SP_HBA_UNX_MSGRJCT 0x09 /* Unexpected message reject */
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#define SP_HBA_RESET_STUCK 0x0a /* SCSI bus reset stuck */
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#define SP_HBA_RSENSE_FAIL 0x0b /* Auto-request sense failed */
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#define SP_HBA_PARITY 0x0c /* HBA memory parity error */
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#define SP_HBA_ABORT_NA 0x0d /* CP aborted - not on bus */
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#define SP_HBA_ABORTED 0x0e /* CP aborted - was on bus */
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#define SP_HBA_RESET_NA 0x0f /* CP reset - not on bus */
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#define SP_HBA_RESET 0x10 /* CP reset - was on bus */
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#define SP_HBA_ECC 0x11 /* HBA memory ECC error */
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#define SP_HBA_PCI_PARITY 0x12 /* PCI parity error */
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#define SP_HBA_PCI_MASTER 0x13 /* PCI master abort */
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#define SP_HBA_PCI_TARGET 0x14 /* PCI target abort */
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#define SP_HBA_PCI_SIG_TARGET 0x15 /* PCI signalled target abort */
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#define SP_HBA_ABORT 0x20 /* Software abort (too many retries) */
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/*
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* Scatter-gather list element.
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*/
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struct eata_sg {
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u_int32_t sg_addr;
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u_int32_t sg_len;
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} __attribute__ ((__packed__));
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/*
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* EATA configuration data as returned by HBA. XXX This is bogus - it
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* doesn't sync up with the structure FreeBSD uses. [ad]
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*/
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struct eata_cfg {
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u_int8_t ec_devtype;
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u_int8_t ec_pagecode;
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u_int8_t ec_reserved0;
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u_int8_t ec_cfglen; /* Length in bytes past here */
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u_int8_t ec_eatasig[4]; /* EATA signature */
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u_int8_t ec_eataversion; /* EATA version number */
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u_int8_t ec_feat0; /* First feature byte */
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u_int8_t ec_padlength[2]; /* Pad bytes for PIO cmds */
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u_int8_t ec_hba[4]; /* Host adapter SCSI IDs */
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u_int8_t ec_cplen[4]; /* Command packet length */
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u_int8_t ec_splen[4]; /* Status packet length */
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u_int8_t ec_queuedepth[2]; /* Controller queue depth */
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u_int8_t ec_reserved1[2];
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u_int8_t ec_sglen[2]; /* Maximum s/g list size */
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u_int8_t ec_feat1; /* 2nd feature byte */
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u_int8_t ec_irq; /* IRQ address */
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u_int8_t ec_feat2; /* 3rd feature byte */
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u_int8_t ec_feat3; /* 4th feature byte */
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u_int8_t ec_maxlun; /* Maximum LUN supported */
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u_int8_t ec_feat4; /* 5th feature byte */
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u_int8_t ec_raidnum; /* RAID host adapter humber */
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} __attribute__ ((__packed__));
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#define EC_F0_OVERLAP_CMDS 0x01 /* Overlapped cmds supported */
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#define EC_F0_TARGET_MODE 0x02 /* Target mode supported */
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#define EC_F0_TRUNC_NOT_REC 0x04 /* Truncate cmd not supported */
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#define EC_F0_MORE_SUPPORTED 0x08 /* More cmd supported */
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#define EC_F0_DMA_SUPPORTED 0x10 /* DMA mode supported */
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#define EC_F0_DMA_NUM_VALID 0x20 /* DMA channel field is valid */
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#define EC_F0_ATA_DEV 0x40 /* This is an ATA device */
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#define EC_F0_HBA_VALID 0x80 /* HBA field is valid */
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#define EC_F1_IRQ_NUM_MASK 0x0f /* IRQ number mask */
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#define EC_F1_IRQ_NUM_SHIFT 0
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#define EC_F1_IRQ_TRIGGER 0x10 /* IRQ trigger: 0 = edge, 1 = level */
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#define EC_F1_SECONDARY 0x20 /* Controller not at address 0x170 */
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#define EC_F1_DMA_NUM_MASK 0xc0 /* DMA channel *index* for ISA */
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#define EC_F1_DMA_NUM_SHIFT 6
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#define EC_F2_ISA_IO_DISABLE 0x01 /* ISA I/O address disabled */
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#define EC_F2_FORCE_ADDR 0x02 /* HBA forced to EISA/ISA address */
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#define EC_F2_SG_64K 0x04 /* 64kB of scatter/gather space */
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#define EC_F2_SG_UNALIGNED 0x08 /* Can do unaligned scatter/gather */
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#define EC_F2_RESERVED0 0x10 /* Reserved */
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#define EC_F2_RESERVED1 0x20 /* Reserved */
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#define EC_F2_RESERVED2 0x40 /* Reserved */
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#define EC_F2_RESERVED3 0x40 /* Reserved */
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#define EC_F3_MAX_TARGET_MASK 0x1f /* Maximum target ID supported */
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#define EC_F3_MAX_TARGET_SHIFT 0
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#define EC_F3_MAX_CHANNEL_MASK 0xe0 /* Maximum channel ID supported */
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#define EC_F3_MAX_CHANNEL_SHIFT 5
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#define EC_F4_RESERVED0 0x01 /* Reserved */
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#define EC_F4_RESERVED1 0x02 /* Reserved */
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#define EC_F4_RESERVED2 0x04 /* Reserved */
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#define EC_F4_AUTO_TERM 0x08 /* Supports auto termination */
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#define EC_F4_PCIM1 0x10 /* PCI M1 chipset */
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#define EC_F4_BOGUS_RAID_ID 0x20 /* RAID ID may be questionable */
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#define EC_F4_HBA_PCI 0x40 /* PCI adapter */
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#define EC_F4_HBA_EISA 0x80 /* EISA adapter */
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/*
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* How SCSI inquiry data breaks down for EATA boards.
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*/
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struct eata_inquiry_data {
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u_int8_t ei_device;
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u_int8_t ei_dev_qual2;
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u_int8_t ei_version;
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u_int8_t ei_response_format;
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u_int8_t ei_additional_length;
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u_int8_t ei_unused[2];
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u_int8_t ei_flags;
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char ei_vendor[8]; /* Vendor, e.g: DPT, NEC */
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char ei_model[7]; /* Model number */
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char ei_suffix[9]; /* Model number suffix */
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char ei_fw[3]; /* Firmware */
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char ei_fwrev[1]; /* Firmware revision */
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u_int8_t ei_extra[8];
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} __attribute__ ((__packed__));
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#endif /* !defined _IC_DPTREG_H_ */
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