138 lines
5.3 KiB
C
138 lines
5.3 KiB
C
/* $NetBSD: hd64461reg.h,v 1.2 2001/06/04 17:08:36 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define SH3_AREA4_BASE 0xb0000000
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#define SH3_AREA5_BASE 0xb4000000
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#define SH3_AREA6_BASE 0xb8000000
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/* HD64461 Address mapping (mapped to SH3 memory space) */
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/* SH3 Area 4 (Register, Framebuffer) */
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#define HD64461_REGBASE SH3_AREA4_BASE
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#define HD64461_REGSIZE 0x02000000
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#define HD64461_FBBASE (SH3_AREA4_BASE + 0x02000000)
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#define HD64461_FBSIZE 0x02000000
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#define HD64461_FBPAGESIZE 0x1000
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/* SH3 Area 5 (PCC1 memory space) */
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#define HD64461_PCC1_MEMBASE SH3_AREA5_BASE
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#define HD64461_PCC1_MEMSIZE 0x02000000
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/* SH3 Area 6 (PCC0 memory, I/O space*/
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#define HD64461_PCC0_MEMBASE SH3_AREA6_BASE
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#define HD64461_PCC0_MEMSIZE 0x02000000
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#define HD64461_PCC0_IOBASE (SH3_AREA6_BASE + 0x02000000)
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#define HD64461_PCC0_IOSIZE 0x02000000
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/*
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* Register mapping.
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*/
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#define HD64461_SYSTEM_REGBASE 0xb0000000
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#define HD64461_SYSTEM_REGSIZE 0x00001000
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#define HD64461_LCDC_REGBASE 0xb0001000
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#define HD64461_LCDC_REGSIZE 0x00001000
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#define HD64461_PCMCIA_REGBASE 0xb0002000
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#define HD64461_PCMCIA_REGSIZE 0x00001000
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#define HD64461_AFE_REGBASE 0xb0003000
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#define HD64461_AFE_REGSIZE 0x00001000
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#define HD64461_GPIO_REGBASE 0xb0004000
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#define HD64461_GPIO_REGSIZE 0x00001000
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#define HD64461_INTC_REGBASE 0xb0005000
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#define HD64461_INTC_REGSIZE 0x00001000
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#define HD64461_TIMER_REGBASE 0xb0006000
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#define HD64461_TIMER_REGSIZE 0x00001000
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#define HD64461_IRDA_REGBASE 0xb0007000
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#define HD64461_IRDA_REGSIZE 0x00001000
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#define HD64461_UART_REGBASE 0xb0008000
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#define HD64461_UART_REGSIZE 0x00001000
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/*
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* System Configuration Register and STANBY Mode
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*/
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/* Stanby Control Register */
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#define HD64461_SYSSTBCR_REG16 0xb0000000
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#define HD64461_SYSSTBCR_CKIO_STBY 0x2000
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#define HD64461_SYSSTBCR_SAFECKE_IST 0x1000
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#define HD64461_SYSSTBCR_SLCKE_IST 0x0800
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#define HD64461_SYSSTBCR_SAFECKE_OST 0x0400
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#define HD64461_SYSSTBCR_SLCKE_OST 0x0200
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#define HD64461_SYSSTBCR_SMIAST 0x0100
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#define HD64461_SYSSTBCR_SLCDST 0x0080
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#define HD64461_SYSSTBCR_SPC0ST 0x0040
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#define HD64461_SYSSTBCR_SPC1ST 0x0020
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#define HD64461_SYSSTBCR_SAFEST 0x0010
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#define HD64461_SYSSTBCR_STM0ST 0x0008
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#define HD64461_SYSSTBCR_STM1ST 0x0004
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#define HD64461_SYSSTBCR_SIRST 0x0002
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#define HD64461_SYSSTBCR_SURTSD 0x0001
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/* System Configuration Register */
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#define HD64461_SYSSYSCR_REG16 0xb0000002
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#define HD64461_SYSSYSCR_SCPU_BUS_IGAT 0x2000
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#define HD64461_SYSSYSCR_SPTA_IR 0x0080
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#define HD64461_SYSSYSCR_SPTA_TM 0x0040
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#define HD64461_SYSSYSCR_SPTB_UR 0x0020
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#define HD64461_SYSSYSCR_WAIT_CTL_SEL 0x0010
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#define HD64461_SYSSYSCR_SMODE1 0x0002
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#define HD64461_SYSSYSCR_SMODE0 0x0001
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/* CPU Data Bus Control Register */
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#define HD64461_SYSSCPUCR_REG16 0xb0000004
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#define HD64461_SYSSCPUCR_SPDSTOF 0x8000
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#define HD64461_SYSSCPUCR_SPDSTIG 0x4000
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#define HD64461_SYSSCPUCR_SPCSTOF 0x2000
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#define HD64461_SYSSCPUCR_SPCSTIG 0x1000
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#define HD64461_SYSSCPUCR_SPBSTOF 0x0800
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#define HD64461_SYSSCPUCR_SPBSTIG 0x0400
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#define HD64461_SYSSCPUCR_SPASTOF 0x0200
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#define HD64461_SYSSCPUCR_SPASTIG 0x0100
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#define HD64461_SYSSCPUCR_SLCDSTIG 0x0080
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#define HD64461_SYSSCPUCR_SCPU_CS56_EP 0x0040
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#define HD64461_SYSSCPUCR_SCPU_CMD_EP 0x0020
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#define HD64461_SYSSCPUCR_SCPU_ADDR_EP 0x0010
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#define HD64461_SYSSCPUCR_SCPDPU 0x0008
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#define HD64461_SYSSCPUCR_SCPU_A2319_EP 0x0001
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