249 lines
7.3 KiB
C
249 lines
7.3 KiB
C
/*-
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* Copyright (c) 2001 SATO Kazumi, All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* definition for identify VR series cpu
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* $NetBSD: vrcpudef.h,v 1.4 2002/02/10 15:09:32 sato Exp $
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*
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* REQUIRE #include "opt_vr41xx.h" before using this header.
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*/
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#include "opt_vr41xx.h"
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/*
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* VR cpu id
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* It is related with BCU cpu id.
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* KEEP consistency with bcureg.h
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*/
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#define VRID_4101 0x0 /* VR4101 */
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#define VRID_4102 0x1 /* VR4102 */
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#define VRID_4111 0x2 /* VR4111 */
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#define VRID_4121 0x3 /* VR4121 */
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#define VRID_4122 0x4 /* VR4122 */
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#define VRID_4131 0x5 /* VR4131 */
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/* conflict other cpu */
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#define VRID_4181 0x10 /* VR4181 conflict VR4101 */
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/*
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* VR cpu architecure group
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*
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* vr41xx group: all vr cpus (some registers are same)
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* vr4181 group: vr4181 (vrip address and registers are same)
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* vr4101 group: vr4101???
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* vr4102 group: vr4102, vr4111, vr4121, vr4122 (some resgiters are same)
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* or vr4102, vr4111, vr4121 (vrip address and registers are same)
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* vr4111 group: vr4111, vr4121, vr4122 (some registers are same)
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* or vr4111, vr4121 (vrip address and registers are same)
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* vr4122 group: vr4122, vr4131 (vrip address and registers are same)
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*
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* REQUIRE #include "opt_vr41xx.h" before using this definition.
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*/
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#if defined VR4181
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#define VRGROUP_4181 VRID_4181
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#endif /* defined VR4181 */
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#if defined VR4101
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#define VRGROUP_4101 VRID_4101
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#endif /* defined VR4101 */
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#if defined VR4102
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#define VRGROUP_4102 VRID_4102
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#define VRGROUP_4102_4121 VRID_4102
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#define VRGROUP_4102_4122 VRID_4102
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#define VRGROUP_4102_4131 VRID_4102
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#endif /* defined VR4102 */
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#if defined VR4111
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#define VRGROUP_4111_4121 VRID_4111
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#define VRGROUP_4111_4122 VRID_4111
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#define VRGROUP_4111_4131 VRID_4111
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#ifndef VRGROUP_4102_4121
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#define VRGROUP_4102_4121 VRID_4111
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#endif /* VRGROUP_4102_4121 */
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#ifndef VRGROUP_4102_4122
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#define VRGROUP_4102_4122 VRID_4111
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#endif /* VRGROUP_4102_4122 */
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#ifndef VRGROUP_4102_4131
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#define VRGROUP_4102_4131 VRID_4111
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#endif /* VRGROUP_4102_4131 */
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#endif /* defined VR4111 */
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#if defined VR4121
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#define VRGROUP_4121_4122 VRID_4121
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#define VRGROUP_4121_4131 VRID_4131
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#ifndef VRGROUP_4111_4121
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#define VRGROUP_4111_4121 VRID_4121
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#endif /* VRGROUP_4111_4121 */
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#ifndef VRGROUP_4111_4122
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#define VRGROUP_4111_4122 VRID_4121
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#endif /* VRGROUP_4111_4122 */
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#ifndef VRGROUP_4111_4131
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#define VRGROUP_4111_4131 VRID_4121
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#endif /* VRGROUP_4111_4131 */
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#ifndef VRGROUP_4102_4121
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#define VRGROUP_4102_4121 VRID_4121
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#endif /* VRGROUP_4102_4121 */
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#ifndef VRGROUP_4102_4122
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#define VRGROUP_4102_4122 VRID_4121
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#endif /* VRGROUP_4102_4122 */
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#ifndef VRGROUP_4102_4131
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#define VRGROUP_4102_4131 VRID_4121
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#endif /* VRGROUP_4102_4131 */
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#endif /* VR4121 */
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#if defined VR4122
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#define VRGROUP_4122 VRID_4122
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#ifndef VRGROUP_4122_4131
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#define VRGROUP_4122_4131 VRID_4122
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#endif /* VRGROUP_4122_4131 */
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#ifndef VRGROUP_4111_4122
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#define VRGROUP_4111_4122 VRID_4122
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#endif /* VRGROUP_4111_4122 */
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#ifndef VRGROUP_4111_4131
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#define VRGROUP_4111_4131 VRID_4122
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#endif /* VRGROUP_4111_4131 */
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#ifndef VRGROUP_4102_4122
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#define VRGROUP_4102_4122 VRID_4122
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#endif /* VRGROUP_4102_4122 */
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#ifndef VRGROUP_4102_4131
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#define VRGROUP_4102_4131 VRID_4122
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#endif /* VRGROUP_4102_4131 */
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#endif /* VR4122 */
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#if defined VR4131
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#define VRGROUP_4131 VRID_4131
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#ifndef VRGROUP_4122_4131
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#define VRGROUP_4122_4131 VRID_4131
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#endif /* VRGROUP_4122_4131 */
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#ifndef VRGROUP_4111_4131
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#define VRGROUP_4111_4131 VRID_4131
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#endif /* VRGROUP_4111_4131 */
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#ifndef VRGROUP_4102_4131
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#define VRGROUP_4102_4131 VRID_4131
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#endif /* VRGROUP_4102_4131 */
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#endif /* VR4131 */
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/*
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* identify one cpu only
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*/
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#if defined VR4181 && !defined VR4101 && !defined VRGROUP_4102_4131
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#define ONLY_VR4181 VRID_4181
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#endif /* ONLY_VR4181 */
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#if !defined VR4181 && defined VR4101 && !defined VRGROUP_4102_4131
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#define ONLY_VR4101 VRID_4101
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#endif /* ONLY_VR4101 */
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#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && defined VR4102 && !defined VRGROUP_4111_4131
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#define ONLY_VR4102 VRID_4102
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#endif /* ONLY_VR4102 */
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#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VR4102 && defined VRGROUP_4111_4121 && !defined VRGROUP_4122_4131
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#define ONLY_VR4111_4121 VRGROUP_4111_4121
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#endif /* ONLY_VR4111_4121 */
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#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VR4122 && !defined VRGROUP_4131
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#define ONLY_VR4122 VRID4122
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#endif /* ONLY_VR4122 */
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#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && !defined VRGROUP_4122 && defined VR4131
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#define ONLY_VR4131 VRID4131
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#endif /* ONLY_VR4131 */
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#if !defined VRGROUP_4181 && !defined VRGROUP_4101 && !defined VRGROUP_4102_4121 && defined VRGROUP_4122_4131
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#define ONLY_VR4122_4131 VRGROUP_4122_4131
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#endif /* ONLY_VR4131 */
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#if defined ONLY_VR4181
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#define ONLY_VR_SPECIFIED ONLY_VR4181
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#endif /* defined ONLY_VR4181 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4101
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#define ONLY_VR_SPECIFIED ONLY_VR4101
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#endif /* defined ONLY_VR4101 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4102
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#define ONLY_VR_SPECIFIED ONLY_VR4102
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#endif /* defined ONLY_VR4102 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4111_4121
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#define ONLY_VR_SPECIFIED ONLY_VR4111_4121
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#endif /* defined ONLY_VR4111_4121 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122_4131
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#define ONLY_VR_SPECIFIED ONLY_VR4122_4131
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#endif /* ONLY_VR4122 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4122
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#define ONLY_VR_SPECIFIED ONLY_VR4122
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#endif /* ONLY_VR4122 */
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#if !defined ONLY_VR_SPECIFIED && defined ONLY_VR4131
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#define ONLY_VR_SPECIFIED ONLY_VR4131
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#endif /* ONLY_VR4131 */
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/*
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* identify single vrip base address
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*/
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#if defined ONLY_VR4181
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#define SINGLE_VRIP_BASE ONLY_VR4181
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#endif /* defined ONLY_VR4181 */
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#if !defined VR4181 && defined VRGROUP_4102_4121 && !defined VRGROUP_4122_4131
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#define SINGLE_VRIP_BASE VRGROUP_4102_4121
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#endif
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#if !defined VR4181 && !defined VRGROUP_4102_4121 && defined VRGROUP_4122_4131
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#define SINGLE_VRIP_BASE VRGROUP_4122_4131
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#endif
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/* end */
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