355 lines
9.9 KiB
C
355 lines
9.9 KiB
C
/* $NetBSD: bhareg.h,v 1.2 1996/09/01 00:54:36 mycroft Exp $ */
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/*
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* Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Originally written by Julian Elischer (julian@tfs.com)
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* for TRW Financial Systems for use under the MACH(2.5) operating system.
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*
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* TRW Financial Systems, in accordance with their agreement with Carnegie
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* Mellon University, makes this software available to CMU to distribute
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* or use in any manner that they see fit as long as this message is kept with
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* the software. For this reason TFS also grants any other persons or
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* organisations permission to use or modify this software.
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*
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* TFS supplies this software to be publicly redistributed
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* on the understanding that TFS is not responsible for the correct
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* functioning of this software in any circumstances.
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*/
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typedef u_int8_t physaddr[4];
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typedef u_int8_t physlen[4];
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#define ltophys _lto4l
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#define phystol _4ltol
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/*
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* I/O port offsets
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*/
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#define BHA_CTRL_PORT 0 /* control (wo) */
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#define BHA_STAT_PORT 0 /* status (ro) */
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#define BHA_CMD_PORT 1 /* command (wo) */
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#define BHA_DATA_PORT 1 /* data (ro) */
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#define BHA_INTR_PORT 2 /* interrupt status (ro) */
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/*
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* BHA_CTRL bits
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*/
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#define BHA_CTRL_HRST 0x80 /* Hardware reset */
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#define BHA_CTRL_SRST 0x40 /* Software reset */
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#define BHA_CTRL_IRST 0x20 /* Interrupt reset */
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#define BHA_CTRL_SCRST 0x10 /* SCSI bus reset */
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/*
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* BHA_STAT bits
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*/
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#define BHA_STAT_STST 0x80 /* Self test in Progress */
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#define BHA_STAT_DIAGF 0x40 /* Diagnostic Failure */
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#define BHA_STAT_INIT 0x20 /* Mbx Init required */
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#define BHA_STAT_IDLE 0x10 /* Host Adapter Idle */
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#define BHA_STAT_CDF 0x08 /* cmd/data out port full */
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#define BHA_STAT_DF 0x04 /* Data in port full */
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#define BHA_STAT_INVDCMD 0x01 /* Invalid command */
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/*
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* BHA_CMD opcodes
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*/
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#define BHA_NOP 0x00 /* No operation */
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#define BHA_MBX_INIT 0x01 /* Mbx initialization */
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#define BHA_START_SCSI 0x02 /* start scsi command */
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#define BHA_INQUIRE_REVISION 0x04 /* Adapter Inquiry */
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#define BHA_MBO_INTR_EN 0x05 /* Enable MBO available interrupt */
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#if 0
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#define BHA_SEL_TIMEOUT_SET 0x06 /* set selection time-out */
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#define BHA_BUS_ON_TIME_SET 0x07 /* set bus-on time */
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#define BHA_BUS_OFF_TIME_SET 0x08 /* set bus-off time */
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#define BHA_SPEED_SET 0x09 /* set transfer speed */
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#endif
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#define BHA_INQUIRE_DEVICES 0x0a /* return installed devices 0-7 */
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#define BHA_INQUIRE_CONFIG 0x0b /* return configuration data */
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#define BHA_TARGET_EN 0x0c /* enable target mode */
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#define BHA_INQUIRE_SETUP 0x0d /* return setup data */
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#define BHA_ECHO 0x1e /* Echo command data */
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#define BHA_INQUIRE_DEVICES_2 0x23 /* return installed devices 8-15 */
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#define BHA_MBX_INIT_EXTENDED 0x81 /* Mbx initialization */
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#define BHA_INQUIRE_REVISION_3 0x84 /* Get 3rd firmware version byte */
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#define BHA_INQUIRE_REVISION_4 0x85 /* Get 4th firmware version byte */
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#define BHA_INQUIRE_MODEL 0x8b /* Get hardware ID and revision */
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#define BHA_INQUIRE_PERIOD 0x8c /* Get synchronous period */
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#define BHA_INQUIRE_EXTENDED 0x8d /* Adapter Setup Inquiry */
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#define BHA_ROUND_ROBIN 0x8f /* Enable/Disable(default) round robin */
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/*
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* BHA_INTR bits
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*/
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#define BHA_INTR_ANYINTR 0x80 /* Any interrupt */
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#define BHA_INTR_SCRD 0x08 /* SCSI reset detected */
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#define BHA_INTR_HACC 0x04 /* Command complete */
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#define BHA_INTR_MBOA 0x02 /* MBX out empty */
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#define BHA_INTR_MBIF 0x01 /* MBX in full */
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struct bha_mbx_out {
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physaddr ccb_addr;
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u_char dummy[3];
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u_char cmd;
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};
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struct bha_mbx_in {
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physaddr ccb_addr;
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u_char dummy[3];
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u_char stat;
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};
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/*
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* mbo.cmd values
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*/
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#define BHA_MBO_FREE 0x0 /* MBO entry is free */
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#define BHA_MBO_START 0x1 /* MBO activate entry */
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#define BHA_MBO_ABORT 0x2 /* MBO abort entry */
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/*
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* mbi.stat values
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*/
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#define BHA_MBI_FREE 0x0 /* MBI entry is free */
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#define BHA_MBI_OK 0x1 /* completed without error */
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#define BHA_MBI_ABORT 0x2 /* aborted ccb */
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#define BHA_MBI_UNKNOWN 0x3 /* Tried to abort invalid CCB */
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#define BHA_MBI_ERROR 0x4 /* Completed with error */
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#if defined(BIG_DMA)
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WARNING...THIS WON'T WORK(won't fit on 1 page)
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#if 0
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#define BHA_NSEG 2048 /* Number of scatter gather segments - to much vm */
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#endif
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#define BHA_NSEG 128
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#else
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#define BHA_NSEG 33
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#endif /* BIG_DMA */
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struct bha_scat_gath {
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physlen seg_len;
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physaddr seg_addr;
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};
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struct bha_ccb {
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u_char opcode;
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u_char:3, data_in:1, data_out:1,:3;
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u_char scsi_cmd_length;
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u_char req_sense_length;
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/*------------------------------------longword boundary */
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physlen data_length;
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/*------------------------------------longword boundary */
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physaddr data_addr;
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/*------------------------------------longword boundary */
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u_char dummy1[2];
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u_char host_stat;
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u_char target_stat;
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/*------------------------------------longword boundary */
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u_char target;
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u_char lun;
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struct scsi_generic scsi_cmd;
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u_char dummy2[1];
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u_char link_id;
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/*------------------------------------longword boundary */
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physaddr link_addr;
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/*------------------------------------longword boundary */
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physaddr sense_ptr;
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/*-----end of HW fields-----------------------longword boundary */
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struct scsi_sense_data scsi_sense;
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/*------------------------------------longword boundary */
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struct bha_scat_gath scat_gath[BHA_NSEG];
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/*------------------------------------longword boundary */
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TAILQ_ENTRY(bha_ccb) chain;
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struct bha_ccb *nexthash;
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long hashkey;
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struct scsi_xfer *xs; /* the scsi_xfer for this cmd */
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int flags;
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#define CCB_ALLOC 0x01
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#define CCB_ABORT 0x02
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#ifdef BHADIAG
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#define CCB_SENDING 0x04
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#endif
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int timeout;
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};
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/*
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* opcode fields
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*/
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#define BHA_INITIATOR_CCB 0x00 /* SCSI Initiator CCB */
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#define BHA_TARGET_CCB 0x01 /* SCSI Target CCB */
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#define BHA_INIT_SCAT_GATH_CCB 0x02 /* SCSI Initiator with scattter gather */
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#define BHA_RESET_CCB 0x81 /* SCSI Bus reset */
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/*
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* bha_ccb.host_stat values
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*/
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#define BHA_OK 0x00 /* cmd ok */
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#define BHA_LINK_OK 0x0a /* Link cmd ok */
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#define BHA_LINK_IT 0x0b /* Link cmd ok + int */
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#define BHA_SEL_TIMEOUT 0x11 /* Selection time out */
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#define BHA_OVER_UNDER 0x12 /* Data over/under run */
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#define BHA_BUS_FREE 0x13 /* Bus dropped at unexpected time */
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#define BHA_INV_BUS 0x14 /* Invalid bus phase/sequence */
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#define BHA_BAD_MBO 0x15 /* Incorrect MBO cmd */
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#define BHA_BAD_CCB 0x16 /* Incorrect ccb opcode */
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#define BHA_BAD_LINK 0x17 /* Not same values of LUN for links */
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#define BHA_INV_TARGET 0x18 /* Invalid target direction */
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#define BHA_CCB_DUP 0x19 /* Duplicate CCB received */
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#define BHA_INV_CCB 0x1a /* Invalid CCB or segment list */
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struct bha_extended_inquire {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char bus_type; /* Type of bus connected to */
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#define BHA_BUS_TYPE_24BIT 'A' /* ISA bus */
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#define BHA_BUS_TYPE_32BIT 'E' /* EISA/VLB/PCI bus */
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#define BHA_BUS_TYPE_MCA 'M' /* MicroChannel bus */
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u_char bios_address; /* Address of adapter BIOS */
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u_short max_segment; /* ? */
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} reply;
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};
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struct bha_config {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char chan;
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u_char intr;
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u_char scsi_dev:3;
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u_char :5;
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} reply;
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};
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struct bha_toggle {
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struct {
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u_char opcode;
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u_char enable;
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} cmd;
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};
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struct bha_mailbox {
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struct {
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u_char opcode;
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u_char nmbx;
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physaddr addr;
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} cmd;
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};
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struct bha_model {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char id[4]; /* i.e bt742a -> '7','4','2','A' */
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u_char version[2]; /* i.e Board Revision 'H' -> 'H', 0x00 */
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} reply;
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};
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struct bha_revision {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char board_type;
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u_char custom_feature;
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char firm_revision;
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u_char firm_version;
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} reply;
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};
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struct bha_digit {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char digit;
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} reply;
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};
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struct bha_devices {
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struct {
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u_char opcode;
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} cmd;
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struct {
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u_char junk[8];
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} reply;
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};
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struct bha_setup {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char sync_neg:1;
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u_char parity:1;
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u_char :6;
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u_char speed;
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u_char bus_on;
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u_char bus_off;
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u_char num_mbx;
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u_char mbx[3]; /*XXX */
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/* doesn't make sense with 32bit addresses */
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struct {
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u_char offset:4;
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u_char period:3;
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u_char valid:1;
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} sync[8];
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u_char disc_sts;
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} reply;
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};
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struct bha_period {
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struct {
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u_char opcode;
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u_char len;
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} cmd;
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struct {
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u_char period[8];
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} reply;
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};
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#define INT9 0x01
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#define INT10 0x02
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#define INT11 0x04
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#define INT12 0x08
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#define INT14 0x20
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#define INT15 0x40
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#define EISADMA 0x00
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#define CHAN0 0x01
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#define CHAN5 0x20
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#define CHAN6 0x40
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#define CHAN7 0x80
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