332 lines
7.8 KiB
C
332 lines
7.8 KiB
C
/* $NetBSD: ieee_invop.c,v 1.2 1996/05/03 23:19:28 phil Exp $ */
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/*
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* IEEE floating point support for NS32081 and NS32381 fpus.
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* Copyright (c) 1995 Ian Dall
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* IAN DALL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION.
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* IAN DALL DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES
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* WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*/
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/*
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* File: ieee_invop.c
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* Author: Ian Dall
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* Date: November 1995
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*
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* Handle operations which generated reserved operand traps.
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*
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* HISTORY
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* 23-Apr-96 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* Don't change sign of NaN operands of NEGF and SUBF.
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*
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* 23-Apr-96 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* Operations on signaling NaN's always produce a quiet NaN.
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*
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* 08-Apr-96 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* Generate correct return value so flags get set properly.
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*
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* 05-Apr-96 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* Get subnormal number divided by subnormal number right.
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* Get infinty multiplied by zero right.
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*
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* 02-Apr-96 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* Make 0/0 produce NaN.
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*
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* 14-Dec-95 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* First release.
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*
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*/
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#include "ieee_internal.h"
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#include <machine/psl.h>
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#include <limits.h>
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static int nan_2(union t_conv data1, union t_conv *data2)
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{
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int nans = (ISNAN(data1)? 1: 0) + (ISNAN(*data2)? 2: 0);
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switch (nans) {
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case 0:
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return 0;
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case 1:
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*data2 = data1;
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break;
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case 2:
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break;
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case 3:
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if((data1.d_bits.mantissa > data2->d_bits.mantissa)
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|| (data1.d_bits.mantissa == data1.d_bits.mantissa
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&& data1.d_bits.mantissa2 > data2->d_bits.mantissa2)) {
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*data2 = data1;
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}
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break;
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}
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data2->d_bits.mantissa |= 0x80000; /* Make sure it is a quiet NaN */
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return 1;
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}
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static int add_iv (struct operand *op1, struct operand *op2)
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{
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int inftys;
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int ret = FPC_TT_NONE;
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if(nan_2(op1->data, &op2->data)) {
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return ret;
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}
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inftys = (ISINFTY(op1->data)? 1: 0) + (ISINFTY(op2->data)? 2:0);
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switch (inftys) {
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case 0:
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break;
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case 1:
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op2->data = op1->data;
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return ret;
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case 2:
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return ret;
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case 3:
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if(op1->data.d_bits.sign != op2->data.d_bits.sign) {
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op2->data = qnan;
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return FPC_TT_INVOP;
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}
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return ret;
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}
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/* Must be subnormals */
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return ieee_add(op1->data.d, &op2->data.d);
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}
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static int div_iv (struct operand *op1, struct operand *op2)
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{
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int inftys, sign1, sign2;
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int ret = FPC_TT_NONE;
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if(nan_2(op1->data, &op2->data)) {
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return ret;
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}
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inftys = (ISINFTY(op1->data)? 1: 0) + (ISINFTY(op2->data)? 2:0);
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sign1 = op1->data.d_bits.sign;
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sign2 = op2->data.d_bits.sign;
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switch (inftys) {
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case 0:
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break;
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case 1: /* n/oo */
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{
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op2->data.d = 0.0;
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op2->data.d_bits.sign = sign1 ^ sign2;
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return ret;
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}
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case 2: /* oo/n */
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op2->data.d_bits.sign = sign1 ^ sign2;
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return ret;
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case 3:
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op2->data = qnan;
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return FPC_TT_INVOP;
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}
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if(ISZERO(op1->data)) {
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if (ISZERO(op2->data)) {
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/* Must be 0/0 */
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op2->data = qnan;
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return FPC_TT_INVOP;
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}
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else {
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/* Must be subnorm/0 */
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op2->data = infty;
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op2->data.d_bits.sign = sign1 ^ sign2;
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return FPC_TT_DIV0;
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}
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}
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/* Must be subnorm/subnorm */
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return ieee_div(op1->data.d, &op2->data.d);
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}
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static int mul_iv (struct operand *op1, struct operand *op2)
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{
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int inftys, sign1, sign2;
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int ret = FPC_TT_NONE;
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if(nan_2(op1->data, &op2->data)) {
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return ret;
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}
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inftys = (ISINFTY(op1->data)? 1: 0) + (ISINFTY(op2->data)? 2:0);
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sign1 = op1->data.d_bits.sign;
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sign2 = op2->data.d_bits.sign;
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switch (inftys) {
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case 0:
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break;
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case 1: /* oo * n */
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if (ISZERO(op2->data)) {
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op2->data = qnan;
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return FPC_TT_INVOP;
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}
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else {
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op2->data = op1->data;
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op2->data.d_bits.sign = sign1 ^ sign2;
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return ret;
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}
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case 2: /* n * oo */
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if (ISZERO(op1->data)) {
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op2->data = qnan;
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return FPC_TT_INVOP;
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}
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/* Fall through */
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case 3: /* oo * oo */
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op2->data.d_bits.sign = sign1 ^ sign2;
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return ret;
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}
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/* Must be subnormals */
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return ieee_mul(op1->data.d, &op2->data.d);
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}
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static int dot_iv (struct operand *op1, struct operand *op2, struct operand *op3)
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{
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int inftys;
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int ret = FPC_TT_NONE;
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union t_conv t = op2->data;
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if(nan_2(op1->data, &t)) {
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if(nan_2(t, &op3->data))
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return ret;
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}
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inftys = ((ISINFTY(op1->data)? 1: 0) + (ISINFTY(op2->data)? 2:0)
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+ (ISINFTY(op3->data)? 4: 0));
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switch (inftys) {
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case 0:
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break;
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case 1: case 2: case 3: /* oo * n + m or n * oo + m or oo * oo + m */
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op3->data = op2->data;
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return mul_iv(op1, op3);
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case 4: /* n * m + oo */
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return ret;
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case 5: case 6: case 7:
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{
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struct operand t = *op2;
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mul_iv(op1, &t);
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add_iv(&t, op3);
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return ret;
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}
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}
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/* Must be subnormals */
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return ieee_dot(op1->data.d, op2->data.d, &op3->data.d);
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}
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static int poly_iv (struct operand *op1, struct operand *op2, struct operand *op3)
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{
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int ret;
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struct operand t = *op2;
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ret = dot_iv(op3, op1, &t);
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*op3 = t;
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return ret;
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}
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static int round_iv (struct operand *op1, struct operand *op2, int xopcode)
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{
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int ret = FPC_TT_NONE;
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if(ISNAN(op1->data)) {
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/* XXX */
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op2->data.i = 0;
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return FPC_TT_INVOP; /* Need a special code */
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}
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else if (ISINFTY(op1->data)) {
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op2->data.i = op1->data.d_bits.sign? INT_MIN: INT_MAX;
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} else {
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/* Must be a denorm */
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op2->data.i = 0;
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}
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return ret;
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}
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static int scalb_iv (struct operand *op1, struct operand *op2)
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{
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int ret = FPC_TT_NONE;
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if(nan_2(op1->data, &op2->data)) {
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return ret;
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}
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return ieee_scalb(op1->data.d, &op2->data.d);
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}
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static int logb_iv (struct operand *op1, struct operand *op2)
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{
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int ret = FPC_TT_NONE;
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if (ISNAN(op1->data))
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op2->data = op1->data;
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else if(ISINFTY(op1->data))
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op2->data = infty;
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else {
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/* Is a denormal */
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union t_conv t = op1->data;
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int norm = ieee_normalize(&t);
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op2->data.d = t.d_bits.exp + norm;
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}
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return ret;
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}
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static void cmp_iv(struct operand *op1, struct operand *op2, state *state)
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{
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state->PSR &= ~(PSR_N | PSR_Z | PSR_L);
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if (ISNAN(op1->data) || ISNAN(op2->data)) {
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return;
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}
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ieee_cmp(op1->data.d, op2->data.d, state);
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return;
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}
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int ieee_invop(struct operand *op1, struct operand *op2,
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struct operand *f0_op, int xopcode, state *state)
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{
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int user_trap = FPC_TT_NONE;
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unsigned int fsr = state->FSR;
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/* Don't fiddle with fsr. The FPC_TT_INVOP bit should only be set
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* if we attempt to *generate* a NaN. This is achieved by returning
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* FPC_TT_INVOP when we generate a NaN.
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*/
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/*
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* Figure out right thing to do.
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*/
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switch(xopcode) {
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case NEGF:
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if(! ISNAN(op1->data))
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op1->data.d_bits.sign ^= 1;
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/* Fall through */
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case MOVF:
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case MOVLF:
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case MOVFL:
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op2->data = op1->data;
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break;
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case CMPF:
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cmp_iv(op1, op2, state);
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break;
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case SUBF:
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if(! ISNAN(op1->data))
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op1->data.d_bits.sign ^= 1;
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/* Fall through */
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case ADDF:
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user_trap = add_iv(op1, op2);
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break;
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case MULF:
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user_trap = mul_iv(op1, op2);
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break;
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case DIVF:
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user_trap = div_iv(op1, op2);
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break;
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case ROUNDFI:
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case TRUNCFI:
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case FLOORFI:
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user_trap = round_iv(op1, op2, xopcode);
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break;
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case SCALBF:
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user_trap = scalb_iv(op1, op2);
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break;
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case LOGBF:
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user_trap = logb_iv(op1, op2);
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break;
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case DOTF:
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user_trap = dot_iv(op1, op2, f0_op);
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break;
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case POLYF:
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user_trap = poly_iv(op1, op2, f0_op);
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break;
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}
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return user_trap;
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}
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