196 lines
6.9 KiB
C
196 lines
6.9 KiB
C
/* $NetBSD: ixp12x0_pcireg.h,v 1.1 2002/07/15 16:27:17 ichiro Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
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* HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXP12X0_PCIREG_H_
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#define _IXP12X0_PCIREG_H_
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#include <arm/ixp12x0/ixp12x0reg.h>
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/* PCI Configuration Space Registers */
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/* base address */
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#define IXP_PCI_MEM_BAR 0x10
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# define IXP1200_PCI_MEM_BAR 0x40000000UL
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#define IXP_PCI_IO_BAR 0x14
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# define IXP1200_PCI_IO_BAR 0x0000f000UL
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#define IXP_PCI_DRAM_BAR 0x18
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# define IXP1200_PCI_DRAM_BAR 0x00000000UL
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#define PCI_CAP_PTR 0x34
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#define PCI_INT_LINE 0x3C
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#define MAILBOX_0 0x50
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#define MAILBOX_1 0x54
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#define MAILBOX_2 0x58
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#define MAILBOX_3 0x5C
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#define DOORBELL 0x60
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#define DOORBELL_SETUP 0x64
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#define ROM_BYTE_WRITE 0x68
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#define CAP_PTR_EXT 0x70
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#define PWR_MGMT 0x74
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/* Reset Registers*/
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#define IXPPCI_IXP1200_RESET 0x7C
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# define RESET_UE0 (1U << 0)
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# define RESET_UE1 (1U << 1)
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# define RESET_UE2 (1U << 2)
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# define RESET_UE3 (1U << 3)
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# define RESET_UE4 (1U << 4)
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# define RESET_UE5 (1U << 5)
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# define RESET_PCIRST (1U << 14)
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# define RESET_EXRST (1U << 15)
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# define RESET_FBI (1U << 16)
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# define RESET_CMDARB (1U << 17)
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# define RESET_SDRAM (1U << 18)
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# define RESET_SRAM (1U << 29)
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# define RESET_PCI (1U << 30)
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# define RESET_SACORE (1U << 31)
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# define RESET_FULL (RESET_UE0 | RESET_UE1 | RESET_UE2 | \
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RESET_UE3 | RESET_UE4 | RESET_UE5 | \
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RESET_EXRST | RESET_FBI | \
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RESET_CMDARB | RESET_SDRAM | RESET_SRAM | \
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RESET_PCI | RESET_SACORE)
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#define CHAN_1_BYTE_COUNT 0x80
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#define CHAN_1_PCI_ADDR 0x84
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#define CHAN_1_DRAM_ADDR 0x88
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#define CHAN_1_DESC_PTR 0x8C
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#define CHAN_1_CONTROL 0x90
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#define DMA_INF_MODE 0x9C
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#define CHAN_2_BYTE_COUNT 0xA0
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#define CHAN_2_PCI_ADDR 0xA4
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#define CHAN_2_DRAM_ADDR 0xA8
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#define CHAN_2_DESC_PTR 0xAC
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#define CHAN_2_CONTROL 0xB0
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#define CSR_BASE_ADDR_MASK 0x0F8
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#define CSR_BASE_ADDR_OFF 0xFC
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# define CSR_BASE_ADDR_MASK_1M 0x000c0000UL
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#define DRAM_BASE_ADDR_MASK 0x100
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#define DRAM_BASE_ADDR_OFF 0x104
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# define DRAM_BASE_ADDR_MASK_256MB 0x0ffc0000UL
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#define ROM_BASE_ADDR_MASK 0x108
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#define DRAM_TIMING 0x10C
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#define DRAM_ADDR_SIZE_0 0x110
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#define DRAM_ADDR_SIZE_1 0x114
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#define DRAM_ADDR_SIZE_2 0x118
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#define DRAM_ADDR_SIZE_3 0x11C
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#define I2O_IFH 0x120
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#define I2O_IPT 0x124
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#define I2O_OPH 0x128
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#define I2O_OFT 0x12C
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#define I2O_IFC 0x130
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#define I2O_OPC 0x134
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#define I2O_IPC 0x138
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#define SA_CONTROL 0x13C
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# define SA_CONTROL_PNR (1 << 9)
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# define SA_CONTROL_COMPLETE (1 << 0)
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#define PCI_ADDR_EXT 0x140
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#define PREFETCH_RANGE 0x144
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#define PCI_ABITOR_STATUS 0x148
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#define DBELL_PCI_MASK 0x150
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#define DBELL_SA_MASK 0x154
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/*
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* Interrupt index assignment
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*
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* FIQ/IRQ bitmap in "PCI Registers Accessible Through StrongARM Core"
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+
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* |D|R|R|D|D|P|I|S|R|S|D|D| |P|D|D|D| |T|T|T|T| |S| |
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* |P|T|M|P|T|W|I|D|S|B|M|M|R|I|M|M|F| |4|3|2|1| |I| |
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* |E|A|A|E|E|R|P|P|E| |A|A|E|L|A|A|H| RES | | | | |RES| | |
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* | | | |D| |M| |A|R| |2|1|S| |2|1| | | | | | | | | |
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* | | | | | | | |R|R| |N|N| | | | | | | | | | | | | |
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* | | | | | | | | | | |B|B| | | | | | | | | | | | | |
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------------+-+-+-+-+---+-+-+
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1
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* index 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 7 6 5 4 1 0
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*
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*/
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/* PCI_IRQ_STATUS */
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#define IXPPCI_IRQ_STATUS (IXP12X0_PCI_VBASE + 0x180)
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#define IXPPCI_FIQ_STATUS (IXP12X0_PCI_VBASE + 0x280)
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#define IXPPCI_IRQ_RAW_STATUS (IXP12X0_PCI_VBASE + 0x184)
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#define IXPPCI_FIQ_RAW_STATUS (IXP12X0_PCI_VBASE + 0x284)
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#define IXPPCI_IRQ_ENABLE (IXP12X0_PCI_VBASE + 0x188)
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#define IXPPCI_FIQ_ENABLE (IXP12X0_PCI_VBASE + 0x288)
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#define IXPPCI_IRQ_ENABLE_SET (IXP12X0_PCI_VBASE + 0x188)
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#define IXPPCI_FIQ_ENABLE_SET (IXP12X0_PCI_VBASE + 0x288)
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#define IXPPCI_IRQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x18c)
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#define IXPPCI_FIQ_ENABLE_CLEAR (IXP12X0_PCI_VBASE + 0x28c)
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#define IXPPCI_IRQ_SOFT (IXP12X0_PCI_VBASE + 0x190)
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#define IXPPCI_FIQ_SOFT (IXP12X0_PCI_VBASE + 0x290)
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#define IXPPCI_IRQST_TIMER (IXP12X0_PCI_VBASE + 0x010)
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#define IXPPCI_INTR_DPE 63
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#define IXPPCI_INTR_RTA 62
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#define IXPPCI_INTR_RMA 61
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#define IXPPCI_INTR_DPED 60
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#define IXPPCI_INTR_DTE 59
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#define IXPPCI_INTR_PWRM 58
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#define IXPPCI_INTR_IIP 57
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#define IXPPCI_INTR_SDPAR 56
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#define IXPPCI_INTR_RSERR 55
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#define IXPPCI_INTR_SB 54
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#define IXPPCI_INTR_DMA2NB 53
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#define IXPPCI_INTR_DMA1NB 52
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#define IXPPCI_INTR_bit19 51
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#define IXPPCI_INTR_PIL 50
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#define IXPPCI_INTR_DMA2 49
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#define IXPPCI_INTR_DMA1 48
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#define IXPPCI_INTR_DFH 47
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#define IXPPCI_INTR_bit14 46
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#define IXPPCI_INTR_bit13 45
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#define IXPPCI_INTR_bit12 44
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#define IXPPCI_INTR_bit11 43
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#define IXPPCI_INTR_bit10 42
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#define IXPPCI_INTR_bit9 41
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#define IXPPCI_INTR_bit8 40
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#define IXPPCI_INTR_T4 39
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#define IXPPCI_INTR_T3 38
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#define IXPPCI_INTR_T2 37
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#define IXPPCI_INTR_T1 36
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#define IXPPCI_INTR_bit3 35
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#define IXPPCI_INTR_bit2 34
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#define IXPPCI_INTR_SI 33
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#define IXPPCI_INTR_bit0 32
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#endif /* _IXP12X0_PCIREG_H_ */
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