1180 lines
27 KiB
C
1180 lines
27 KiB
C
/* $NetBSD: cpu.c,v 1.60 2011/07/16 14:46:18 rmind Exp $ */
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/* NetBSD: cpu.c,v 1.18 2004/02/20 17:35:01 yamt Exp */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* Copyright (c) 2002, 2006, 2007 YAMAMOTO Takashi,
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by RedBack Networks Inc.
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*
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* Author: Bill Sommerfeld
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999 Stefan Grefen
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR AND CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.60 2011/07/16 14:46:18 rmind Exp $");
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#include "opt_ddb.h"
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#include "opt_multiprocessor.h"
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#include "opt_mpbios.h" /* for MPDEBUG */
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#include "opt_mtrr.h"
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#include "opt_xen.h"
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#include "lapic.h"
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#include "ioapic.h"
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kmem.h>
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#include <sys/cpu.h>
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#include <sys/atomic.h>
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#include <sys/reboot.h>
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#include <uvm/uvm.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuvar.h>
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#include <machine/pmap.h>
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#include <machine/vmparam.h>
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#include <machine/mpbiosvar.h>
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#include <machine/pcb.h>
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#include <machine/specialreg.h>
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#include <machine/segments.h>
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#include <machine/gdt.h>
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#include <machine/mtrr.h>
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#include <machine/pio.h>
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#include <xen/vcpuvar.h>
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#if NLAPIC > 0
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#include <machine/apicvar.h>
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#include <machine/i82489reg.h>
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#include <machine/i82489var.h>
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#endif
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#include <dev/ic/mc146818reg.h>
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#include <dev/isa/isareg.h>
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#if MAXCPUS > 32
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#error cpu_info contains 32bit bitmasks
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#endif
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static int cpu_match(device_t, cfdata_t, void *);
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static void cpu_attach(device_t, device_t, void *);
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static void cpu_defer(device_t);
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static int cpu_rescan(device_t, const char *, const int *);
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static void cpu_childdetached(device_t, device_t);
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static int vcpu_match(device_t, cfdata_t, void *);
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static void vcpu_attach(device_t, device_t, void *);
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static void cpu_attach_common(device_t, device_t, void *);
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void cpu_offline_md(void);
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struct cpu_softc {
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device_t sc_dev; /* device tree glue */
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struct cpu_info *sc_info; /* pointer to CPU info */
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bool sc_wasonline;
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};
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int mp_cpu_start(struct cpu_info *, paddr_t);
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void mp_cpu_start_cleanup(struct cpu_info *);
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const struct cpu_functions mp_cpu_funcs = { mp_cpu_start, NULL,
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mp_cpu_start_cleanup };
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CFATTACH_DECL2_NEW(cpu, sizeof(struct cpu_softc),
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cpu_match, cpu_attach, NULL, NULL, cpu_rescan, cpu_childdetached);
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CFATTACH_DECL_NEW(vcpu, sizeof(struct cpu_softc),
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vcpu_match, vcpu_attach, NULL, NULL);
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/*
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* Statically-allocated CPU info for the primary CPU (or the only
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* CPU, on uniprocessors). The CPU info list is initialized to
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* point at it.
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*/
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#ifdef TRAPLOG
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#include <machine/tlog.h>
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struct tlog tlog_primary;
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#endif
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struct cpu_info cpu_info_primary __aligned(CACHE_LINE_SIZE) = {
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.ci_dev = 0,
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.ci_self = &cpu_info_primary,
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.ci_idepth = -1,
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.ci_curlwp = &lwp0,
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.ci_curldt = -1,
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.ci_cpumask = 1,
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#ifdef TRAPLOG
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.ci_tlog = &tlog_primary,
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#endif
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};
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struct cpu_info phycpu_info_primary __aligned(CACHE_LINE_SIZE) = {
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.ci_dev = 0,
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.ci_self = &phycpu_info_primary,
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};
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struct cpu_info *cpu_info_list = &cpu_info_primary;
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struct cpu_info *phycpu_info_list = &phycpu_info_primary;
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static void cpu_set_tss_gates(struct cpu_info *ci);
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uint32_t cpus_attached = 1;
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uint32_t cpus_running = 1;
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uint32_t phycpus_attached = 0;
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uint32_t phycpus_running = 0;
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uint32_t cpu_feature[5]; /* X86 CPUID feature bits
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* [0] basic features %edx
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* [1] basic features %ecx
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* [2] extended features %edx
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* [3] extended features %ecx
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* [4] VIA padlock features
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*/
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bool x86_mp_online;
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paddr_t mp_trampoline_paddr = MP_TRAMPOLINE;
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#if defined(MULTIPROCESSOR)
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void cpu_hatch(void *);
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static void cpu_boot_secondary(struct cpu_info *ci);
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static void cpu_start_secondary(struct cpu_info *ci);
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static void cpu_copy_trampoline(void);
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/*
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* Runs once per boot once multiprocessor goo has been detected and
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* the local APIC on the boot processor has been mapped.
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*
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* Called from lapic_boot_init() (from mpbios_scan()).
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*/
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void
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cpu_init_first(void)
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{
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cpu_info_primary.ci_cpuid = lapic_cpu_number();
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cpu_copy_trampoline();
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}
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#endif /* MULTIPROCESSOR */
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static int
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cpu_match(device_t parent, cfdata_t match, void *aux)
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{
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return 1;
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}
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static void
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cpu_attach(device_t parent, device_t self, void *aux)
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{
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struct cpu_softc *sc = device_private(self);
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struct cpu_attach_args *caa = aux;
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struct cpu_info *ci;
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uintptr_t ptr;
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static int nphycpu = 0;
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sc->sc_dev = self;
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if (phycpus_attached == ~0) {
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aprint_error(": increase MAXCPUS\n");
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return;
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}
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/*
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* If we're an Application Processor, allocate a cpu_info
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* If we're the first attached CPU use the primary cpu_info,
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* otherwise allocate a new one
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*/
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aprint_naive("\n");
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aprint_normal("\n");
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if (nphycpu > 0) {
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struct cpu_info *tmp;
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ptr = (uintptr_t)kmem_zalloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
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KM_SLEEP);
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ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE);
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ci->ci_curldt = -1;
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tmp = phycpu_info_list;
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while (tmp->ci_next)
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tmp = tmp->ci_next;
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tmp->ci_next = ci;
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} else {
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ci = &phycpu_info_primary;
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}
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ci->ci_self = ci;
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sc->sc_info = ci;
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ci->ci_dev = self;
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ci->ci_acpiid = caa->cpu_id;
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ci->ci_cpuid = caa->cpu_number;
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ci->ci_vcpu = NULL;
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ci->ci_index = nphycpu++;
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ci->ci_cpumask = (1 << cpu_index(ci));
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atomic_or_32(&phycpus_attached, ci->ci_cpumask);
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if (!pmf_device_register(self, NULL, NULL))
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aprint_error_dev(self, "couldn't establish power handler\n");
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(void)config_defer(self, cpu_defer);
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}
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static void
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cpu_defer(device_t self)
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{
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cpu_rescan(self, NULL, NULL);
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}
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static int
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cpu_rescan(device_t self, const char *ifattr, const int *locators)
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{
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struct cpu_softc *sc = device_private(self);
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struct cpufeature_attach_args cfaa;
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struct cpu_info *ci = sc->sc_info;
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memset(&cfaa, 0, sizeof(cfaa));
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cfaa.ci = ci;
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if (ifattr_match(ifattr, "cpufeaturebus")) {
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if (ci->ci_frequency == NULL) {
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cfaa.name = "frequency";
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ci->ci_frequency = config_found_ia(self,
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"cpufeaturebus", &cfaa, NULL);
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}
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}
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return 0;
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}
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static void
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cpu_childdetached(device_t self, device_t child)
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{
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struct cpu_softc *sc = device_private(self);
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struct cpu_info *ci = sc->sc_info;
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if (ci->ci_frequency == child)
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ci->ci_frequency = NULL;
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}
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static int
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vcpu_match(device_t parent, cfdata_t match, void *aux)
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{
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struct vcpu_attach_args *vcaa = aux;
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if (strcmp(vcaa->vcaa_name, match->cf_name) == 0)
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return 1;
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return 0;
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}
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static void
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vcpu_attach(device_t parent, device_t self, void *aux)
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{
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struct vcpu_attach_args *vcaa = aux;
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cpu_attach_common(parent, self, &vcaa->vcaa_caa);
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}
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static void
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cpu_vm_init(struct cpu_info *ci)
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{
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int ncolors = 2, i;
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for (i = CAI_ICACHE; i <= CAI_L2CACHE; i++) {
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struct x86_cache_info *cai;
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int tcolors;
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cai = &ci->ci_cinfo[i];
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tcolors = atop(cai->cai_totalsize);
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switch(cai->cai_associativity) {
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case 0xff:
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tcolors = 1; /* fully associative */
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break;
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case 0:
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case 1:
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break;
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default:
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tcolors /= cai->cai_associativity;
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}
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ncolors = max(ncolors, tcolors);
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}
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/*
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* Knowing the size of the largest cache on this CPU, re-color
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* our pages.
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*/
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if (ncolors <= uvmexp.ncolors)
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return;
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aprint_debug_dev(ci->ci_dev, "%d page colors\n", ncolors);
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uvm_page_recolor(ncolors);
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}
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static void
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cpu_attach_common(device_t parent, device_t self, void *aux)
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{
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struct cpu_softc *sc = device_private(self);
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struct cpu_attach_args *caa = aux;
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struct cpu_info *ci;
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uintptr_t ptr;
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int cpunum = caa->cpu_number;
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static bool again = false;
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sc->sc_dev = self;
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/*
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* If we're an Application Processor, allocate a cpu_info
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* structure, otherwise use the primary's.
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*/
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if (caa->cpu_role == CPU_ROLE_AP) {
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aprint_naive(": Application Processor\n");
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ptr = (uintptr_t)kmem_alloc(sizeof(*ci) + CACHE_LINE_SIZE - 1,
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KM_SLEEP);
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ci = (struct cpu_info *)roundup2(ptr, CACHE_LINE_SIZE);
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memset(ci, 0, sizeof(*ci));
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#ifdef TRAPLOG
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ci->ci_tlog_base = kmem_zalloc(sizeof(struct tlog), KM_SLEEP);
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#endif
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} else {
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aprint_naive(": %s Processor\n",
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caa->cpu_role == CPU_ROLE_SP ? "Single" : "Boot");
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ci = &cpu_info_primary;
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#if NLAPIC > 0
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if (cpunum != lapic_cpu_number()) {
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/* XXX should be done earlier */
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uint32_t reg;
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aprint_verbose("\n");
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aprint_verbose_dev(self, "running CPU at apic %d"
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" instead of at expected %d", lapic_cpu_number(),
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cpunum);
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reg = i82489_readreg(LAPIC_ID);
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i82489_writereg(LAPIC_ID, (reg & ~LAPIC_ID_MASK) |
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(cpunum << LAPIC_ID_SHIFT));
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}
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if (cpunum != lapic_cpu_number()) {
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aprint_error_dev(self, "unable to reset apic id\n");
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}
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#endif
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}
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ci->ci_self = ci;
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sc->sc_info = ci;
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ci->ci_dev = self;
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ci->ci_cpuid = cpunum;
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KASSERT(HYPERVISOR_shared_info != NULL);
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ci->ci_vcpu = &HYPERVISOR_shared_info->vcpu_info[cpunum];
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ci->ci_func = caa->cpu_func;
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/* Must be called before mi_cpu_attach(). */
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cpu_vm_init(ci);
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if (caa->cpu_role == CPU_ROLE_AP) {
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int error;
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error = mi_cpu_attach(ci);
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if (error != 0) {
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aprint_normal("\n");
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aprint_error_dev(self,
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"mi_cpu_attach failed with %d\n", error);
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return;
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}
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} else {
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KASSERT(ci->ci_data.cpu_idlelwp != NULL);
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}
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ci->ci_cpumask = (1 << cpu_index(ci));
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pmap_reference(pmap_kernel());
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ci->ci_pmap = pmap_kernel();
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ci->ci_tlbstate = TLBSTATE_STALE;
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/*
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* Boot processor may not be attached first, but the below
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* must be done to allow booting other processors.
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*/
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if (!again) {
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atomic_or_32(&ci->ci_flags, CPUF_PRESENT | CPUF_PRIMARY);
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/* Basic init. */
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cpu_intr_init(ci);
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cpu_get_tsc_freq(ci);
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cpu_init(ci);
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cpu_set_tss_gates(ci);
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#if NLAPIC > 0
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if (caa->cpu_role != CPU_ROLE_SP) {
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/* Enable lapic. */
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lapic_enable();
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lapic_set_lvt();
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lapic_calibrate_timer();
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}
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#endif
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/* Make sure DELAY() is initialized. */
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DELAY(1);
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again = true;
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}
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|
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/* further PCB init done later. */
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switch (caa->cpu_role) {
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case CPU_ROLE_SP:
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atomic_or_32(&ci->ci_flags, CPUF_SP);
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cpu_identify(ci);
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#if 0
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x86_errata();
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#endif
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x86_cpu_idle_init();
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break;
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case CPU_ROLE_BP:
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atomic_or_32(&ci->ci_flags, CPUF_BSP);
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cpu_identify(ci);
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cpu_init(ci);
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#if 0
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x86_errata();
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#endif
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x86_cpu_idle_init();
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break;
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case CPU_ROLE_AP:
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/*
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* report on an AP
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*/
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#if defined(MULTIPROCESSOR)
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cpu_intr_init(ci);
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gdt_alloc_cpu(ci);
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cpu_set_tss_gates(ci);
|
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cpu_start_secondary(ci);
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if (ci->ci_flags & CPUF_PRESENT) {
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struct cpu_info *tmp;
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identifycpu(ci);
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tmp = cpu_info_list;
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|
while (tmp->ci_next)
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tmp = tmp->ci_next;
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|
|
|
tmp->ci_next = ci;
|
|
}
|
|
#else
|
|
aprint_error_dev(self, "not started\n");
|
|
#endif
|
|
break;
|
|
|
|
default:
|
|
aprint_normal("\n");
|
|
panic("unknown processor type??\n");
|
|
}
|
|
|
|
pat_init(ci);
|
|
atomic_or_32(&cpus_attached, ci->ci_cpumask);
|
|
|
|
#if 0
|
|
if (!pmf_device_register(self, cpu_suspend, cpu_resume))
|
|
aprint_error_dev(self, "couldn't establish power handler\n");
|
|
#endif
|
|
|
|
#if defined(MULTIPROCESSOR)
|
|
if (mp_verbose) {
|
|
struct lwp *l = ci->ci_data.cpu_idlelwp;
|
|
struct pcb *pcb = lwp_getpcb(l);
|
|
|
|
aprint_verbose_dev(self,
|
|
"idle lwp at %p, idle sp at 0x%p\n",
|
|
l,
|
|
#ifdef i386
|
|
(void *)pcb->pcb_esp
|
|
#else
|
|
(void *)pcb->pcb_rsp
|
|
#endif
|
|
);
|
|
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Initialize the processor appropriately.
|
|
*/
|
|
|
|
void
|
|
cpu_init(struct cpu_info *ci)
|
|
{
|
|
|
|
/*
|
|
* On a P6 or above, enable global TLB caching if the
|
|
* hardware supports it.
|
|
*/
|
|
if (cpu_feature[0] & CPUID_PGE)
|
|
lcr4(rcr4() | CR4_PGE); /* enable global TLB caching */
|
|
|
|
#ifdef XXXMTRR
|
|
/*
|
|
* On a P6 or above, initialize MTRR's if the hardware supports them.
|
|
*/
|
|
if (cpu_feature[0] & CPUID_MTRR) {
|
|
if ((ci->ci_flags & CPUF_AP) == 0)
|
|
i686_mtrr_init_first();
|
|
mtrr_init_cpu(ci);
|
|
}
|
|
#endif
|
|
/*
|
|
* If we have FXSAVE/FXRESTOR, use them.
|
|
*/
|
|
if (cpu_feature[0] & CPUID_FXSR) {
|
|
lcr4(rcr4() | CR4_OSFXSR);
|
|
|
|
/*
|
|
* If we have SSE/SSE2, enable XMM exceptions.
|
|
*/
|
|
if (cpu_feature[0] & (CPUID_SSE|CPUID_SSE2))
|
|
lcr4(rcr4() | CR4_OSXMMEXCPT);
|
|
}
|
|
|
|
#ifdef __x86_64__
|
|
/* No user PGD mapped for this CPU yet */
|
|
ci->ci_xen_current_user_pgd = 0;
|
|
#endif
|
|
|
|
atomic_or_32(&cpus_running, ci->ci_cpumask);
|
|
atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
|
|
}
|
|
|
|
|
|
#ifdef MULTIPROCESSOR
|
|
void
|
|
cpu_boot_secondary_processors(void)
|
|
{
|
|
struct cpu_info *ci;
|
|
u_long i;
|
|
|
|
for (i = 0; i < maxcpus; i++) {
|
|
ci = cpu_lookup(i);
|
|
if (ci == NULL)
|
|
continue;
|
|
if (ci->ci_data.cpu_idlelwp == NULL)
|
|
continue;
|
|
if ((ci->ci_flags & CPUF_PRESENT) == 0)
|
|
continue;
|
|
if (ci->ci_flags & (CPUF_BSP|CPUF_SP|CPUF_PRIMARY))
|
|
continue;
|
|
cpu_boot_secondary(ci);
|
|
}
|
|
|
|
x86_mp_online = true;
|
|
}
|
|
|
|
static void
|
|
cpu_init_idle_lwp(struct cpu_info *ci)
|
|
{
|
|
struct lwp *l = ci->ci_data.cpu_idlelwp;
|
|
struct pcb *pcb = lwp_getpcb(l);
|
|
|
|
pcb->pcb_cr0 = rcr0();
|
|
}
|
|
|
|
void
|
|
cpu_init_idle_lwps(void)
|
|
{
|
|
struct cpu_info *ci;
|
|
u_long i;
|
|
|
|
for (i = 0; i < maxcpus; i++) {
|
|
ci = cpu_lookup(i);
|
|
if (ci == NULL)
|
|
continue;
|
|
if (ci->ci_data.cpu_idlelwp == NULL)
|
|
continue;
|
|
if ((ci->ci_flags & CPUF_PRESENT) == 0)
|
|
continue;
|
|
cpu_init_idle_lwp(ci);
|
|
}
|
|
}
|
|
|
|
void
|
|
cpu_start_secondary(struct cpu_info *ci)
|
|
{
|
|
int i;
|
|
struct pmap *kpm = pmap_kernel();
|
|
extern uint32_t mp_pdirpa;
|
|
|
|
mp_pdirpa = kpm->pm_pdirpa; /* XXX move elsewhere, not per CPU. */
|
|
|
|
atomic_or_32(&ci->ci_flags, CPUF_AP);
|
|
|
|
aprint_debug_dev(ci->ci_dev, "starting\n");
|
|
|
|
ci->ci_curlwp = ci->ci_data.cpu_idlelwp;
|
|
if (CPU_STARTUP(ci, mp_trampoline_paddr) != 0)
|
|
return;
|
|
|
|
/*
|
|
* wait for it to become ready
|
|
*/
|
|
for (i = 100000; (!(ci->ci_flags & CPUF_PRESENT)) && i > 0; i--) {
|
|
#ifdef MPDEBUG
|
|
extern int cpu_trace[3];
|
|
static int otrace[3];
|
|
if (memcmp(otrace, cpu_trace, sizeof(otrace)) != 0) {
|
|
aprint_debug_dev(ci->ci_dev, "trace %02x %02x %02x\n",
|
|
cpu_trace[0], cpu_trace[1], cpu_trace[2]);
|
|
memcpy(otrace, cpu_trace, sizeof(otrace));
|
|
}
|
|
#endif
|
|
delay(10);
|
|
}
|
|
if ((ci->ci_flags & CPUF_PRESENT) == 0) {
|
|
aprint_error_dev(ci->ci_dev, "failed to become ready\n");
|
|
#if defined(MPDEBUG) && defined(DDB)
|
|
printf("dropping into debugger; continue from here to resume boot\n");
|
|
Debugger();
|
|
#endif
|
|
}
|
|
|
|
CPU_START_CLEANUP(ci);
|
|
}
|
|
|
|
void
|
|
cpu_boot_secondary(struct cpu_info *ci)
|
|
{
|
|
int i;
|
|
|
|
atomic_or_32(&ci->ci_flags, CPUF_GO);
|
|
for (i = 100000; (!(ci->ci_flags & CPUF_RUNNING)) && i > 0; i--) {
|
|
delay(10);
|
|
}
|
|
if ((ci->ci_flags & CPUF_RUNNING) == 0) {
|
|
aprint_error_dev(ci->ci_dev, "CPU failed to start\n");
|
|
#if defined(MPDEBUG) && defined(DDB)
|
|
printf("dropping into debugger; continue from here to resume boot\n");
|
|
Debugger();
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The CPU ends up here when its ready to run
|
|
* This is called from code in mptramp.s; at this point, we are running
|
|
* in the idle pcb/idle stack of the new CPU. When this function returns,
|
|
* this processor will enter the idle loop and start looking for work.
|
|
*
|
|
* XXX should share some of this with init386 in machdep.c
|
|
*/
|
|
void
|
|
cpu_hatch(void *v)
|
|
{
|
|
struct cpu_info *ci = (struct cpu_info *)v;
|
|
struct pcb *pcb;
|
|
int s, i;
|
|
|
|
cpu_probe(ci);
|
|
|
|
cpu_feature[0] &= ~CPUID_FEAT_BLACKLIST;
|
|
cpu_feature[2] &= ~CPUID_FEAT_EXT_BLACKLIST;
|
|
|
|
cpu_init_msrs(ci, true);
|
|
|
|
KDASSERT((ci->ci_flags & CPUF_PRESENT) == 0);
|
|
atomic_or_32(&ci->ci_flags, CPUF_PRESENT);
|
|
while ((ci->ci_flags & CPUF_GO) == 0) {
|
|
/* Don't use delay, boot CPU may be patching the text. */
|
|
for (i = 10000; i != 0; i--)
|
|
x86_pause();
|
|
}
|
|
|
|
/* Because the text may have been patched in x86_patch(). */
|
|
wbinvd();
|
|
x86_flush();
|
|
tlbflushg();
|
|
|
|
KASSERT((ci->ci_flags & CPUF_RUNNING) == 0);
|
|
|
|
pcb = lwp_getpcb(curlwp);
|
|
lcr3(pmap_kernel()->pm_pdirpa);
|
|
pcb->pcb_cr3 = pmap_kernel()->pm_pdirpa;
|
|
pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp);
|
|
lcr0(pcb->pcb_cr0);
|
|
|
|
cpu_init_idt();
|
|
gdt_init_cpu(ci);
|
|
lapic_enable();
|
|
lapic_set_lvt();
|
|
lapic_initclocks();
|
|
|
|
#ifdef i386
|
|
npxinit(ci);
|
|
#else
|
|
fpuinit(ci);
|
|
#endif
|
|
|
|
lldt(GSEL(GLDT_SEL, SEL_KPL));
|
|
ltr(ci->ci_tss_sel);
|
|
|
|
cpu_init(ci);
|
|
cpu_get_tsc_freq(ci);
|
|
|
|
s = splhigh();
|
|
#ifdef i386
|
|
lapic_tpr = 0;
|
|
#else
|
|
lcr8(0);
|
|
#endif
|
|
x86_enable_intr();
|
|
splx(s);
|
|
#if 0
|
|
x86_errata();
|
|
#endif
|
|
|
|
aprint_debug_dev(ci->ci_dev, "CPU %ld running\n",
|
|
(long)ci->ci_cpuid);
|
|
}
|
|
|
|
#if defined(DDB)
|
|
|
|
#include <ddb/db_output.h>
|
|
#include <machine/db_machdep.h>
|
|
|
|
/*
|
|
* Dump CPU information from ddb.
|
|
*/
|
|
void
|
|
cpu_debug_dump(void)
|
|
{
|
|
struct cpu_info *ci;
|
|
CPU_INFO_ITERATOR cii;
|
|
|
|
db_printf("addr dev id flags ipis curlwp fpcurlwp\n");
|
|
for (CPU_INFO_FOREACH(cii, ci)) {
|
|
db_printf("%p %s %ld %x %x %10p %10p\n",
|
|
ci,
|
|
ci->ci_dev == NULL ? "BOOT" : device_xname(ci->ci_dev),
|
|
(long)ci->ci_cpuid,
|
|
ci->ci_flags, ci->ci_ipis,
|
|
ci->ci_curlwp,
|
|
ci->ci_fpcurlwp);
|
|
}
|
|
}
|
|
#endif /* DDB */
|
|
|
|
static void
|
|
cpu_copy_trampoline(void)
|
|
{
|
|
/*
|
|
* Copy boot code.
|
|
*/
|
|
extern u_char cpu_spinup_trampoline[];
|
|
extern u_char cpu_spinup_trampoline_end[];
|
|
|
|
vaddr_t mp_trampoline_vaddr;
|
|
|
|
mp_trampoline_vaddr = uvm_km_alloc(kernel_map, PAGE_SIZE, 0,
|
|
UVM_KMF_VAONLY);
|
|
|
|
pmap_kenter_pa(mp_trampoline_vaddr, mp_trampoline_paddr,
|
|
VM_PROT_READ | VM_PROT_WRITE, 0);
|
|
pmap_update(pmap_kernel());
|
|
memcpy((void *)mp_trampoline_vaddr,
|
|
cpu_spinup_trampoline,
|
|
cpu_spinup_trampoline_end - cpu_spinup_trampoline);
|
|
|
|
pmap_kremove(mp_trampoline_vaddr, PAGE_SIZE);
|
|
pmap_update(pmap_kernel());
|
|
uvm_km_free(kernel_map, mp_trampoline_vaddr, PAGE_SIZE, UVM_KMF_VAONLY);
|
|
}
|
|
|
|
#endif /* MULTIPROCESSOR */
|
|
|
|
#ifdef i386
|
|
#if 0
|
|
static void
|
|
tss_init(struct i386tss *tss, void *stack, void *func)
|
|
{
|
|
memset(tss, 0, sizeof *tss);
|
|
tss->tss_esp0 = tss->tss_esp = (int)((char *)stack + USPACE - 16);
|
|
tss->tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
|
|
tss->__tss_cs = GSEL(GCODE_SEL, SEL_KPL);
|
|
tss->tss_fs = GSEL(GCPU_SEL, SEL_KPL);
|
|
tss->tss_gs = tss->__tss_es = tss->__tss_ds =
|
|
tss->__tss_ss = GSEL(GDATA_SEL, SEL_KPL);
|
|
tss->tss_cr3 = pmap_kernel()->pm_pdirpa;
|
|
tss->tss_esp = (int)((char *)stack + USPACE - 16);
|
|
tss->tss_ldt = GSEL(GLDT_SEL, SEL_KPL);
|
|
tss->__tss_eflags = PSL_MBO | PSL_NT; /* XXX not needed? */
|
|
tss->__tss_eip = (int)func;
|
|
}
|
|
#endif
|
|
|
|
/* XXX */
|
|
#define IDTVEC(name) __CONCAT(X, name)
|
|
typedef void (vector)(void);
|
|
extern vector IDTVEC(tss_trap08);
|
|
#ifdef DDB
|
|
extern vector Xintrddbipi;
|
|
extern int ddb_vec;
|
|
#endif
|
|
|
|
static void
|
|
cpu_set_tss_gates(struct cpu_info *ci)
|
|
{
|
|
#if 0
|
|
struct segment_descriptor sd;
|
|
|
|
ci->ci_doubleflt_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
|
|
UVM_KMF_WIRED);
|
|
tss_init(&ci->ci_doubleflt_tss, ci->ci_doubleflt_stack,
|
|
IDTVEC(tss_trap08));
|
|
setsegment(&sd, &ci->ci_doubleflt_tss, sizeof(struct i386tss) - 1,
|
|
SDT_SYS386TSS, SEL_KPL, 0, 0);
|
|
ci->ci_gdt[GTRAPTSS_SEL].sd = sd;
|
|
setgate(&idt[8], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
|
|
GSEL(GTRAPTSS_SEL, SEL_KPL));
|
|
#endif
|
|
|
|
#if defined(DDB) && defined(MULTIPROCESSOR)
|
|
/*
|
|
* Set up separate handler for the DDB IPI, so that it doesn't
|
|
* stomp on a possibly corrupted stack.
|
|
*
|
|
* XXX overwriting the gate set in db_machine_init.
|
|
* Should rearrange the code so that it's set only once.
|
|
*/
|
|
ci->ci_ddbipi_stack = (char *)uvm_km_alloc(kernel_map, USPACE, 0,
|
|
UVM_KMF_WIRED);
|
|
tss_init(&ci->ci_ddbipi_tss, ci->ci_ddbipi_stack,
|
|
Xintrddbipi);
|
|
|
|
setsegment(&sd, &ci->ci_ddbipi_tss, sizeof(struct i386tss) - 1,
|
|
SDT_SYS386TSS, SEL_KPL, 0, 0);
|
|
ci->ci_gdt[GIPITSS_SEL].sd = sd;
|
|
|
|
setgate(&idt[ddb_vec], NULL, 0, SDT_SYSTASKGT, SEL_KPL,
|
|
GSEL(GIPITSS_SEL, SEL_KPL));
|
|
#endif
|
|
}
|
|
#else
|
|
static void
|
|
cpu_set_tss_gates(struct cpu_info *ci)
|
|
{
|
|
|
|
}
|
|
#endif /* i386 */
|
|
|
|
int
|
|
mp_cpu_start(struct cpu_info *ci, paddr_t target)
|
|
{
|
|
#if 0
|
|
#if NLAPIC > 0
|
|
int error;
|
|
#endif
|
|
unsigned short dwordptr[2];
|
|
|
|
/*
|
|
* Bootstrap code must be addressable in real mode
|
|
* and it must be page aligned.
|
|
*/
|
|
KASSERT(target < 0x10000 && target % PAGE_SIZE == 0);
|
|
|
|
/*
|
|
* "The BSP must initialize CMOS shutdown code to 0Ah ..."
|
|
*/
|
|
|
|
outb(IO_RTC, NVRAM_RESET);
|
|
outb(IO_RTC+1, NVRAM_RESET_JUMP);
|
|
|
|
/*
|
|
* "and the warm reset vector (DWORD based at 40:67) to point
|
|
* to the AP startup code ..."
|
|
*/
|
|
|
|
dwordptr[0] = 0;
|
|
dwordptr[1] = target >> 4;
|
|
|
|
pmap_kenter_pa (0, 0, VM_PROT_READ|VM_PROT_WRITE, 0);
|
|
pmap_update(pmap_kernel());
|
|
|
|
memcpy ((uint8_t *) 0x467, dwordptr, 4);
|
|
|
|
pmap_kremove (0, PAGE_SIZE);
|
|
pmap_update(pmap_kernel());
|
|
|
|
#if NLAPIC > 0
|
|
/*
|
|
* ... prior to executing the following sequence:"
|
|
*/
|
|
|
|
if (ci->ci_flags & CPUF_AP) {
|
|
if ((error = x86_ipi_init(ci->ci_cpuid)) != 0)
|
|
return error;
|
|
|
|
delay(10000);
|
|
|
|
if (cpu_feature & CPUID_APIC) {
|
|
error = x86_ipi_init(ci->ci_cpuid);
|
|
if (error != 0) {
|
|
aprint_error_dev(ci->ci_dev, "%s: IPI not taken (1)\n",
|
|
__func__);
|
|
return error;
|
|
}
|
|
|
|
delay(10000);
|
|
|
|
error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
|
|
LAPIC_DLMODE_STARTUP);
|
|
if (error != 0) {
|
|
aprint_error_dev(ci->ci_dev, "%s: IPI not taken (2)\n",
|
|
__func__);
|
|
return error;
|
|
}
|
|
delay(200);
|
|
|
|
error = x86_ipi(target / PAGE_SIZE, ci->ci_cpuid,
|
|
LAPIC_DLMODE_STARTUP);
|
|
if (error != 0) {
|
|
aprint_error_dev(ci->ci_dev, "%s: IPI not taken ((3)\n",
|
|
__func__);
|
|
return error;
|
|
}
|
|
delay(200);
|
|
}
|
|
}
|
|
#endif
|
|
#endif /* 0 */
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
mp_cpu_start_cleanup(struct cpu_info *ci)
|
|
{
|
|
#if 0
|
|
/*
|
|
* Ensure the NVRAM reset byte contains something vaguely sane.
|
|
*/
|
|
|
|
outb(IO_RTC, NVRAM_RESET);
|
|
outb(IO_RTC+1, NVRAM_RESET_RST);
|
|
#endif
|
|
}
|
|
|
|
void
|
|
cpu_init_msrs(struct cpu_info *ci, bool full)
|
|
{
|
|
#ifdef __x86_64__
|
|
if (full) {
|
|
HYPERVISOR_set_segment_base (SEGBASE_FS, 0);
|
|
HYPERVISOR_set_segment_base (SEGBASE_GS_KERNEL, (uint64_t) ci);
|
|
HYPERVISOR_set_segment_base (SEGBASE_GS_USER, 0);
|
|
}
|
|
#endif /* __x86_64__ */
|
|
|
|
if (cpu_feature[2] & CPUID_NOX)
|
|
wrmsr(MSR_EFER, rdmsr(MSR_EFER) | EFER_NXE);
|
|
}
|
|
|
|
void
|
|
cpu_offline_md(void)
|
|
{
|
|
int s;
|
|
|
|
s = splhigh();
|
|
#ifdef __i386__
|
|
npxsave_cpu(true);
|
|
#else
|
|
fpusave_cpu(true);
|
|
#endif
|
|
splx(s);
|
|
}
|
|
|
|
#if 0
|
|
/* XXX joerg restructure and restart CPUs individually */
|
|
static bool
|
|
cpu_suspend(device_t dv, const pmf_qual_t *qual)
|
|
{
|
|
struct cpu_softc *sc = device_private(dv);
|
|
struct cpu_info *ci = sc->sc_info;
|
|
int err;
|
|
|
|
if (ci->ci_flags & CPUF_PRIMARY)
|
|
return true;
|
|
if (ci->ci_data.cpu_idlelwp == NULL)
|
|
return true;
|
|
if ((ci->ci_flags & CPUF_PRESENT) == 0)
|
|
return true;
|
|
|
|
sc->sc_wasonline = !(ci->ci_schedstate.spc_flags & SPCF_OFFLINE);
|
|
|
|
if (sc->sc_wasonline) {
|
|
mutex_enter(&cpu_lock);
|
|
err = cpu_setstate(ci, false);
|
|
mutex_exit(&cpu_lock);
|
|
|
|
if (err)
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool
|
|
cpu_resume(device_t dv, const pmf_qual_t *qual)
|
|
{
|
|
struct cpu_softc *sc = device_private(dv);
|
|
struct cpu_info *ci = sc->sc_info;
|
|
int err = 0;
|
|
|
|
if (ci->ci_flags & CPUF_PRIMARY)
|
|
return true;
|
|
if (ci->ci_data.cpu_idlelwp == NULL)
|
|
return true;
|
|
if ((ci->ci_flags & CPUF_PRESENT) == 0)
|
|
return true;
|
|
|
|
if (sc->sc_wasonline) {
|
|
mutex_enter(&cpu_lock);
|
|
err = cpu_setstate(ci, true);
|
|
mutex_exit(&cpu_lock);
|
|
}
|
|
|
|
return err == 0;
|
|
}
|
|
#endif
|
|
|
|
void
|
|
cpu_get_tsc_freq(struct cpu_info *ci)
|
|
{
|
|
const volatile vcpu_time_info_t *tinfo = &ci->ci_vcpu->time;
|
|
delay(1000000);
|
|
uint64_t freq = 1000000000ULL << 32;
|
|
freq = freq / (uint64_t)tinfo->tsc_to_system_mul;
|
|
if ( tinfo->tsc_shift < 0 )
|
|
freq = freq << -tinfo->tsc_shift;
|
|
else
|
|
freq = freq >> tinfo->tsc_shift;
|
|
ci->ci_data.cpu_cc_freq = freq;
|
|
}
|
|
|
|
void
|
|
x86_cpu_idle_xen(void)
|
|
{
|
|
struct cpu_info *ci = curcpu();
|
|
|
|
KASSERT(ci->ci_ilevel == IPL_NONE);
|
|
|
|
x86_disable_intr();
|
|
if (!__predict_false(ci->ci_want_resched)) {
|
|
idle_block();
|
|
} else {
|
|
x86_enable_intr();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Loads pmap for the current CPU.
|
|
*/
|
|
void
|
|
cpu_load_pmap(struct pmap *pmap)
|
|
{
|
|
#ifdef i386
|
|
#ifdef PAE
|
|
int i, s;
|
|
struct cpu_info *ci;
|
|
|
|
s = splvm(); /* just to be safe */
|
|
ci = curcpu();
|
|
paddr_t l3_pd = xpmap_ptom_masked(ci->ci_pae_l3_pdirpa);
|
|
/* don't update the kernel L3 slot */
|
|
for (i = 0 ; i < PDP_SIZE - 1; i++) {
|
|
xpq_queue_pte_update(l3_pd + i * sizeof(pd_entry_t),
|
|
xpmap_ptom(pmap->pm_pdirpa[i]) | PG_V);
|
|
}
|
|
splx(s);
|
|
tlbflush();
|
|
#else /* PAE */
|
|
lcr3(pmap_pdirpa(pmap, 0));
|
|
#endif /* PAE */
|
|
#endif /* i386 */
|
|
|
|
#ifdef __x86_64__
|
|
int i, s;
|
|
pd_entry_t *old_pgd, *new_pgd;
|
|
paddr_t addr;
|
|
struct cpu_info *ci;
|
|
|
|
/* kernel pmap always in cr3 and should never go in user cr3 */
|
|
if (pmap_pdirpa(pmap, 0) != pmap_pdirpa(pmap_kernel(), 0)) {
|
|
ci = curcpu();
|
|
/*
|
|
* Map user space address in kernel space and load
|
|
* user cr3
|
|
*/
|
|
s = splvm();
|
|
new_pgd = pmap->pm_pdir;
|
|
old_pgd = pmap_kernel()->pm_pdir;
|
|
addr = xpmap_ptom(pmap_pdirpa(pmap_kernel(), 0));
|
|
for (i = 0; i < PDIR_SLOT_PTE;
|
|
i++, addr += sizeof(pd_entry_t)) {
|
|
if ((new_pgd[i] & PG_V) || (old_pgd[i] & PG_V))
|
|
xpq_queue_pte_update(addr, new_pgd[i]);
|
|
}
|
|
xen_set_user_pgd(pmap_pdirpa(pmap, 0));
|
|
ci->ci_xen_current_user_pgd = pmap_pdirpa(pmap, 0);
|
|
tlbflush();
|
|
splx(s);
|
|
}
|
|
#endif /* __x86_64__ */
|
|
}
|