321 lines
12 KiB
C
321 lines
12 KiB
C
/* $NetBSD: pm2reg.h,v 1.6 2012/02/02 07:09:53 macallan Exp $ */
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/*
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* Copyright (c) 2009 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* register definitions for Permedia 2 graphics controllers
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*/
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#ifndef PM2_REG_H
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#define PM2_REG_H
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#define PM2_RESET 0x00000000 /* any write initiates a chip reset */
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#define PM2_RESET_BUSY 0x80000000 /* reset in progress */
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#define PM2_INPUT_FIFO_SPACE 0x00000018
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#define PM2_OUTPUT_FIFO_WORDS 0x00000020
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#define PM2_VCLKCTL 0x00000040
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#define VCC_CLOCK_A 0x00000000
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#define VCC_CLOCK_B 0x00000001
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#define VCC_CLOCK_C 0x00000002
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/* PCI clocks to wait between RAMDAC accesses */
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#define VCC_RAMDAC_WAIT_MASK 0x000003fc
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#define PM2_APERTURE1_CONTROL 0x00000050
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#define PM2_APERTURE2_CONTROL 0x00000058
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#define PM2_AP_BYTESWAP 0x00000001
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#define PM2_AP_HALFWORDSWAP 0x00000002
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#define PM2_AP_PACKED16_EN 0x00000008
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#define PM2_AP_PACKED16_READ_B 0x00000010 /* Buffer A otherwise */
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#define PM2_AP_PACKED16_WRITE_B 0x00000020 /* A otherwise */
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#define PM2_AP_PACKED16_WRT_DBL 0x00000040
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#define PM2_AP_PACKED16_R31 0x00000080 /* read buffer selected by
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* visibility bit in memory
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*/
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#define PM2_AP_SVGA 0x00000100
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#define PM2_AP_ROM 0x00000200
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#define PM2_BYPASS_MASK 0x00001100
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#define PM2_FB_WRITE_MASK 0x00001140
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#define PM2_OUTPUT_FIFO 0x00002000
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#define PM2_SCREEN_BASE 0x00003000 /* in 64bit units */
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#define PM2_SCREEN_STRIDE 0x00003008 /* in 64bit units */
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#define PM2_HTOTAL 0x00003010
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#define PM2_HGATE_END 0x00003018
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#define PM2_HBLANK_END 0x00003020
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#define PM2_HSYNC_START 0x00003028
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#define PM2_HSYNC_END 0x00003030
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#define PM2_VTOTAL 0x00003038
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#define PM2_VBLANK_END 0x00003040
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#define PM2_VSYNC_START 0x00003048
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#define PM2_VSYNC_END 0x00003050
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#define PM2_VIDEO_CONTROL 0x00003058
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#define PM2_VC_VIDEO_ENABLE 0x00000001
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#define PM2_VC_BLANK_ACR_LOW 0x00000002
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#define PM2_VC_LINE_DOUBLE 0x00000004
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#define PM2_VC_HSYNC_FORCE_H 0x00000000
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#define PM2_VC_HSYNC_ACT_HIGH 0x00000008
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#define PM2_VC_HSYNC_FORCE_L 0x00000010
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#define PM2_VC_HSYNC_ACT_LOW 0x00000018
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#define PM2_VC_VSYNC_FORCE_H 0x00000000
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#define PM2_VC_VSYNC_ACT_HIGH 0x00000020
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#define PM2_VC_VSYNC_FORCE_L 0x00000040
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#define PM2_VC_VSYNC_ACT_LOW 0x00000060
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#define PM2_VC_BP_BASE_PENDING 0x00000080
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#define PM2_VC_RE_BASE_PENDING 0x00000100
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#define PM2_VC_SWAP_SYNC_BLANK 0x00000000
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#define PM2_VC_SWAP_FREERUNNING 0x00000200
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#define PM2_VC_SWAP_LIMIT_FR 0x00000400
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#define PM2_VC_STEREO_ENABLE 0x00000800
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#define PM2_VC_RIGHT_EYE_ACT_L 0x00001000
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#define PM2_VC_DISP_RIGHT_FRAME 0x00002000 /* RO, left otherwise */
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#define PM2_VC_BP_RIGHT_PENDING 0x00004000
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#define PM2_VC_RE_RIGHT_PENDING 0x00008000
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#define PM2_VC_RAMDAC_64BIT 0x00010000 /* 32bit otherwise */
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#define PM2_DISPLAY_DATA 0x00003068
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#define PM2_DD_SDA_IN 0x00000001
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#define PM2_DD_SCL_IN 0x00000002
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#define PM2_DD_SDA_OUT 0x00000004
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#define PM2_DD_SCL_OUT 0x00000008
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#define PM2_DD_LATCHED_DATA 0x00000010
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#define PM2_DD_DATA_VALID 0x00000020 /* clear by 1 */
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#define PM2_DD_START 0x00000040 /* START detected */
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#define PM2_DD_STOP 0x00000080 /* STOP detected */
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#define PM2_DD_INSERT_WAITS 0x00000100
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#define PM2_DD_USE_MONID 0x00000200 /* DDC2 otherwise */
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#define PM2_DD_MONID_IN_MASK 0x00001c00
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#define PM2_DD_MONID_OUT_MASK 0x0000e000
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/* RAMDAC */
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#define PM2_DAC_PAL_WRITE_IDX 0x00004000
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#define PM2_DAC_DATA 0x00004008
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#define PM2_DAC_MASK 0x00004010
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#define PM2_DAC_PAL_READ_IDX 0x00004018
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/* these are different on PM2V: */
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#define PM2_DAC_CURSOR_PAL 0x00004020
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#define PM2_DAC_CURSOR_DATA 0x00004028
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/* here we go: */
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#define PM2V_DAC_INDEX_LOW 0x00004020
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#define PM2V_DAC_INDEX_HIGH 0x00004028
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#define PM2V_DAC_INDEX_DATA 0x00004030
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#define PM2V_DAC_INDEX_CONTROL 0x00004038
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#define PM2_DAC_INDEX_DATA 0x00004050
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#define PM2_DAC_CURSOR_RAM 0x00004058
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#define PM2_DAC_CURSOR_X_LOW 0x00004060
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#define PM2_DAC_CURSOR_X_HIGH 0x00004068
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#define PM2_DAC_CURSOR_Y_LOW 0x00004070
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#define PM2_DAC_CURSOR_Y_HIGH 0x00004078
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/* RAMDAC registers ( through INDEX_DATA */
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#define PM2_DAC_COLOR_MODE 0x18
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#define CM_PALETTE 0x00
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#define CM_RGB332 0x01
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#define CM_RGB232OFFSET 0x02
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#define CM_RGBA2321 0x03
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#define CM_RGBA5551 0x04
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#define CM_RGBA4444 0x05
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#define CM_RGB565 0x06
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#define CM_RGBA8888 0x08
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#define CM_RGB888 0x09
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#define CM_GUI_DISABLE 0x10
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#define CM_RGB 0x20 /* BGR otherwise */
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#define CM_TRUECOLOR 0x80 /* use palette for gamma correction */
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#define PM2_DAC_MISC_CONTROL 0x1e
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#define MC_POWERDOWN 0x01
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#define MC_PALETTE_8BIT 0x02 /* 6bit otherwise */
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#define MC_HSYNC_INV 0x04
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#define MC_VSYNC_INV 0x08
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#define MC_SYNCONGREEN 0x10
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#define PM2_DAC_PIXELCLKA_M 0x20
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#define PM2_DAC_PIXELCLKA_N 0x21
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#define PM2_DAC_PIXELCLKA_P 0x22
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#define PCLK_ENABLE 0x08
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#define PM2_DAC_PIXELCLKB_M 0x23
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#define PM2_DAC_PIXELCLKB_N 0x24
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#define PM2_DAC_PIXELCLKB_P 0x25
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#define PM2_DAC_PIXELCLKC_M 0x26
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#define PM2_DAC_PIXELCLKC_N 0x27
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#define PM2_DAC_PIXELCLKC_P 0x28
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#define PM2_DAC_PIXELCLK_STATUS 0x29
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#define PCLK_LOCKED 0x10
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#define PM2_DAC_MEMCLK_M 0x30
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#define PM2_DAC_MEMCLK_N 0x31
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#define PM2_DAC_MEMCLK_P 0x32
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#define PM2_DAC_MEMCLK_STATUS 0x33
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/* PM2V RAMDAC */
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#define PM2V_DAC_MISC_CONTROL 0x000
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#define PM2V_DAC_8BIT 0x01 /* 6bit otherwise */
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#define PM2V_DAC_BYPASS_CLUT 0x08 /* ??? guess from xorg */
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#define PM2V_DAC_8_24_OVERLAY 0x10 /* ??? guess from xorg */
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#define PM2V_DAC_SYNC_CONTROL 0x001
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#define PM2V_DAC_HSYNC_INV 0x01
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#define PM2V_DAC_VSYNC_INV 0x08
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#define PM2V_DAC_CONTROL 0x002
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#define PM2V_DAC_PIXEL_SIZE 0x003
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#define PM2V_PS_8BIT 0x00
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#define PM2V_PS_16BIT 0x01
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#define PM2V_PS_32BIT 0x02
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#define PM2V_PS_24BIT 0x04
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#define PM2V_DAC_COLOR_FORMAT 0x004
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#define PM2V_DAC_PALETTE 0x2e
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#define PM2V_DAC_RGB555 0x61
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#define PM2V_DAC_RGB565 0x70
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#define PM2V_DAC_RGB888 0x60
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#define PM2V_DAC_RGBA8888 0x20
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#define PM2V_DAC_CHECK_CONTROL 0x018
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#define PM2V_DAC_CLOCK_CONTROL 0x200
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#define PM2V_DAC_CLOCK_A_M 0x201
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#define PM2V_DAC_CLOCK_A_N 0x202
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#define PM2V_DAC_CLOCK_A_P 0x203
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#define PM2V_DAC_CLOCK_B_M 0x204
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#define PM2V_DAC_CLOCK_B_N 0x205
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#define PM2V_DAC_CLOCK_B_P 0x206
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#define PM2V_DAC_MCLK_CONTROL 0x20D
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#define PM2V_DAC_MCLK_M 0x20E
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#define PM2V_DAC_MCLK_N 0x20F
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#define PM2V_DAC_MCLK_P 0x210
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/* drawing engine */
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#define PM2_RE_STARTXDOM 0x00008000
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#define PM2_RE_DXDOM 0x00008008
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#define PM2_RE_STARTXSUB 0x00008010
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#define PM2_RE_STARTY 0x00008020
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#define PM2_RE_DY 0x00008028
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#define PM2_RE_COUNT 0x00008030
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#define PM2_RE_BITMASK 0x00008068 /* for colour expansion */
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#define PM2_RE_COLOUR 0x000087f0
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#define PM2_RE_CONFIG 0x00008d90
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#define PM2RECFG_READ_SRC 0x00000001
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#define PM2RECFG_READ_DST 0x00000002
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#define PM2RECFG_PACKED 0x00000004
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#define PM2RECFG_WRITE_EN 0x00000008
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#define PM2RECFG_DDA_EN 0x00000010
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#define PM2RECFG_ROP_EN 0x00000020
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#define PM2RECFG_ROP_MASK 0x000003c0
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#define PM2RECFG_ROP_SHIFT 6
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#define PM2_RE_CONST_COLOUR 0x000087e8
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#define PM2_RE_BUFFER_OFFSET 0x00008a90 /* distance between src and dst */
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#define PM2_RE_SOURCE_BASE 0x00008d80 /* write after windowbase */
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#define PM2_RE_SOURCE_DELTA 0x00008d88 /* offset in coordinates */
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#define PM2_RE_SOURCE_OFFSET 0x00008a88 /* same in pixels */
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#define PM2_RE_WINDOW_BASE 0x00008ab0
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#define PM2_RE_WINDOW_ORIGIN 0x000081c8
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#define PM2_RE_WRITE_MODE 0x00008ab8
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#define PM2WM_WRITE_EN 0x00000001
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#define PM2WM_TO_HOST 0x00000008
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#define PM2_RE_MODE 0x000080a0
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#define PM2RM_MASK_MIRROR 0x00000001 /* mask is right-to-left */
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#define PM2RM_MASK_INVERT 0x00000002
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#define PM2RM_MASK_OPAQUE 0x00000040 /* BG in TEXEL0 */
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#define PM2RM_MASK_SWAP 0x00000180
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#define PM2RM_MASK_PAD 0x00000200 /* new line new mask */
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#define PM2RM_MASK_OFFSET 0x00007c00
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#define PM2RM_HOST_SWAP 0x00018000
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#define PM2RM_LIMITS_EN 0x00040000
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#define PM2RM_MASK_REL_X 0x00080000
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#define PM2_RE_RECT_START 0x000080d0
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#define PM2_RE_RECT_SIZE 0x000080d8
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#define PM2_RE_RENDER 0x00008038 /* write starts command */
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#define PM2RE_STIPPLE 0x00000001
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#define PM2RE_FASTFILL 0x00000008
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#define PM2RE_LINE 0x00000000
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#define PM2RE_TRAPEZOID 0x00000040
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#define PM2RE_POINT 0x00000080
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#define PM2RE_RECTANGLE 0x000000c0
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#define PM2RE_SYNC_ON_MASK 0x00000800 /* wait for write to bitmask
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register */
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#define PM2RE_SYNC_ON_HOST 0x00001000 /* wait for host data */
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#define PM2RE_TEXTURE_EN 0x00002000
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#define PM2RE_INC_X 0x00200000 /* drawing direction */
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#define PM2RE_INC_Y 0x00400000
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#define PM2_RE_TEXEL0 0x00008600 /* background colour */
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#define PM2_RE_STATUS 0x00000068
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#define PM2ST_BUSY 0x80000000
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#define PM2_RE_SYNC 0x00008c40
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#define PM2_RE_FILTER_MODE 0x00008c00
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#define PM2FLT_PASS_SYNC 0x00000400
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#define PM2_RE_DDA_MODE 0x000087e0
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#define PM2DDA_ENABLE 0x00000001
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#define PM2DDA_GOURAUD 0x00000002 /* flat otherwise */
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#define PM2_RE_BLOCK_COLOUR 0x00008ac8
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#define PM2_RE_STIPPLE_MODE 0x000081a0
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#define PM2ST_ENABLE 0x00000001
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#define PM2ST_XOFFSET_MASK 0x00000380
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#define PM2ST_YOFFSET_MASK 0x00007000
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#define PM2ST_INVERT 0x00020000
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#define PM2ST_MIRROR_X 0x00040000
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#define PM2ST_MIRROR_Y 0x00080000
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#define PM2ST_OPAQUE 0x00100000
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#define PM2_HW_WRITEMASK 0x00008ac0
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#define PM2_SW_WRITEMASK 0x00008820
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#define PM2_FB_READMODE 0x00008a80
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#define PM2FB_PP0_MASK 0x00000007
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#define PM2FB_PP1_MASK 0x00000038
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#define PM2FB_PP2_MASK 0x000001c0
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#define PM2FB_READ_SRC 0x00000200
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#define PM2FB_READ_DST 0x00000400
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#define PM2FB_FBCOLOR 0x00008000 /* for uploads */
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#define PM2FB_ORIGIN_BL 0x00010000 /* window origin, TL otherwise */
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#define PM2FB_PATCH_EN 0x00020000
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#define PM2FB_PACKED 0x00040000
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#define PM2FB_OFFSET_M 0x00380000
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#define PM2FB_PM_PATCH 0x00000000
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#define PM2FB_PM_SUB 0x02000000
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#define PM2FB_PM_SUBP 0x04000000
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#define PM2_RE_SCISSOR_MODE 0x00008180
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#define PM2SC_USER_EN 0x00000001 /* from scissor reg */
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#define PM2SC_SCREEN_EN 0x00000002 /* screensize reg */
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#define PM2_RE_SCREENSIZE 0x00008198
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#define PM2_RE_SCISSOR_MINYX 0x00008188
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#define PM2_RE_SCISSOR_MAXYX 0x00008190
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#define PM2_RE_TEXMAP_FORMAT 0x00008588
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#define PM2_RE_DITHER_MODE 0x00008818
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#define PM2_RE_ALPHA_MODE 0x00008810
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#define PM2_RE_TEX_COLOUR_MODE 0x00008680
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#define PM2_RE_TEX_READ_MODE 0x00008670
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#define PM2_RE_TEX_LUT_MODE 0x00008678
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#define PM2_RE_TEX_ADDRESS_MODE 0x00008380
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#define PM2_RE_YUV_MODE 0x00008f00
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#define PM2_RE_DEPTH_MODE 0x000089a0
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#define PM2_RE_DEPTH 0x000089a8
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#define PM2_RE_STENCIL_MODE 0x00008988
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#define PM2_RE_ROP_MODE 0x00008828
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#endif /* PM2_REG_H */
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