205 lines
7.4 KiB
C
205 lines
7.4 KiB
C
/* $NetBSD: uhcireg.h,v 1.17 2006/03/10 17:18:54 jmcneill Exp $ */
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/* $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.12 1999/11/17 22:33:42 n_hibma Exp $ */
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/*
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson (lennart@augustsson.net) at
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* Carlstedt Research & Technology.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_UHCIREG_H_
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#define _DEV_PCI_UHCIREG_H_
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/*** PCI config registers ***/
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#define PCI_USBREV 0x60 /* USB protocol revision */
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#define PCI_USBREV_MASK 0xff
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#define PCI_USBREV_PRE_1_0 0x00
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#define PCI_USBREV_1_0 0x10
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#define PCI_USBREV_1_1 0x11
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#define PCI_LEGSUP 0xc0 /* Legacy Support register */
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#define PCI_LEGSUP_A20PTS 0x8000 /* End of A20GATE passthru status */
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#define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
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#define PCI_LEGSUP_USBIRQS 0x1000 /* USB IRQ status */
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#define PCI_LEGSUP_TBY64W 0x0800 /* Trap by 64h write status */
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#define PCI_LEGSUP_TBY64R 0x0400 /* Trap by 64h read status */
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#define PCI_LEGSUP_TBY60W 0x0200 /* Trap by 60h write status */
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#define PCI_LEGSUP_TBY60R 0x0100 /* Trap by 60h read status */
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#define PCI_LEGSUP_SMIEPTE 0x0080 /* SMI at end of passthru enable */
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#define PCI_LEGSUP_PSS 0x0040 /* Passthru status */
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#define PCI_LEGSUP_A20PTEN 0x0020 /* A20GATE passthru enable */
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#define PCI_LEGSUP_USBSMIEN 0x0010 /* Enable SMI# generation */
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#define PCI_CBIO 0x20 /* configuration base IO */
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#define PCI_INTERFACE_UHCI 0x00
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/*** UHCI registers ***/
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#define UHCI_CMD 0x00
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#define UHCI_CMD_RS 0x0001
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#define UHCI_CMD_HCRESET 0x0002
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#define UHCI_CMD_GRESET 0x0004
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#define UHCI_CMD_EGSM 0x0008
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#define UHCI_CMD_FGR 0x0010
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#define UHCI_CMD_SWDBG 0x0020
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#define UHCI_CMD_CF 0x0040
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#define UHCI_CMD_MAXP 0x0080
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#define UHCI_STS 0x02
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#define UHCI_STS_USBINT 0x0001
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#define UHCI_STS_USBEI 0x0002
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#define UHCI_STS_RD 0x0004
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#define UHCI_STS_HSE 0x0008
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#define UHCI_STS_HCPE 0x0010
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#define UHCI_STS_HCH 0x0020
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#define UHCI_STS_ALLINTRS 0x003f
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#define UHCI_INTR 0x04
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#define UHCI_INTR_TOCRCIE 0x0001
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#define UHCI_INTR_RIE 0x0002
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#define UHCI_INTR_IOCE 0x0004
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#define UHCI_INTR_SPIE 0x0008
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#define UHCI_FRNUM 0x06
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#define UHCI_FRNUM_MASK 0x03ff
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#define UHCI_FLBASEADDR 0x08
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#define UHCI_SOF 0x0c
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#define UHCI_SOF_MASK 0x7f
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#define UHCI_PORTSC1 0x010
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#define UHCI_PORTSC2 0x012
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#define UHCI_PORTSC_CCS 0x0001
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#define UHCI_PORTSC_CSC 0x0002
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#define UHCI_PORTSC_PE 0x0004
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#define UHCI_PORTSC_POEDC 0x0008
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#define UHCI_PORTSC_LS 0x0030
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#define UHCI_PORTSC_LS_SHIFT 4
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#define UHCI_PORTSC_RD 0x0040
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#define UHCI_PORTSC_LSDA 0x0100
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#define UHCI_PORTSC_PR 0x0200
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#define UHCI_PORTSC_OCI 0x0400
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#define UHCI_PORTSC_OCIC 0x0800
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#define UHCI_PORTSC_SUSP 0x1000
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#define URWMASK(x) \
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((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE))
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#define UHCI_FRAMELIST_COUNT 1024
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#define UHCI_FRAMELIST_ALIGN 4096
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#define UHCI_TD_ALIGN 16
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#define UHCI_QH_ALIGN 16
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typedef u_int32_t uhci_physaddr_t;
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#define UHCI_PTR_T 0x00000001
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#define UHCI_PTR_TD 0x00000000
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#define UHCI_PTR_QH 0x00000002
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#define UHCI_PTR_VF 0x00000004
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/*
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* Wait this long after a QH has been removed. This gives that HC a
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* chance to stop looking at it before it's recycled.
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*/
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#define UHCI_QH_REMOVE_DELAY 5
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/*
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* The Queue Heads and Transfer Descriptors are accessed
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* by both the CPU and the USB controller which run
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* concurrently. This means that they have to be accessed
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* with great care. As long as the data structures are
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* not linked into the controller's frame list they cannot
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* be accessed by it and anything goes. As soon as a
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* TD is accessible by the controller it "owns" the td_status
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* field; it will not be written by the CPU. Similarly
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* the controller "owns" the qh_elink field.
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*/
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typedef struct {
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uhci_physaddr_t td_link;
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u_int32_t td_status;
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#define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff)
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#define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff)
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#define UHCI_TD_BITSTUFF 0x00020000
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#define UHCI_TD_CRCTO 0x00040000
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#define UHCI_TD_NAK 0x00080000
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#define UHCI_TD_BABBLE 0x00100000
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#define UHCI_TD_DBUFFER 0x00200000
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#define UHCI_TD_STALLED 0x00400000
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#define UHCI_TD_ACTIVE 0x00800000
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#define UHCI_TD_IOC 0x01000000
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#define UHCI_TD_IOS 0x02000000
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#define UHCI_TD_LS 0x04000000
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#define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3)
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#define UHCI_TD_SET_ERRCNT(n) ((n) << 27)
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#define UHCI_TD_SPD 0x20000000
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u_int32_t td_token;
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#define UHCI_TD_PID_IN 0x00000069
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#define UHCI_TD_PID_OUT 0x000000e1
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#define UHCI_TD_PID_SETUP 0x0000002d
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#define UHCI_TD_GET_PID(s) ((s) & 0xff)
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#define UHCI_TD_SET_DEVADDR(a) ((a) << 8)
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#define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f)
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#define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15)
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#define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf)
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#define UHCI_TD_SET_DT(t) ((t) << 19)
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#define UHCI_TD_GET_DT(s) (((s) >> 19) & 1)
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#define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21)
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#define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff)
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#define UHCI_TD_MAXLEN_MASK 0xffe00000
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u_int32_t td_buffer;
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} uhci_td_t;
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#define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED)
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#define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \
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UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP)
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#define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
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UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \
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UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt))
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#define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
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UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \
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UHCI_TD_SET_DT(dt))
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typedef struct {
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uhci_physaddr_t qh_hlink;
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uhci_physaddr_t qh_elink;
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} uhci_qh_t;
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#endif /* _DEV_PCI_UHCIREG_H_ */
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