f6cc829138
IDE controllers, which are more-or-less compatible with the AMD controllers. XXX Need to determine the correct timing value for the nForce2 XXX at Ultra133, so we cap it at Ultra100, for now.
95 lines
3.5 KiB
C
95 lines
3.5 KiB
C
/* $NetBSD: pciidevar.h,v 1.8 2003/01/24 04:53:14 thorpej Exp $ */
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/*
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* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI IDE driver exported software structures.
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*
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* Author: Christopher G. Demetriou, March 2, 1998.
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*/
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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struct device;
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struct pciide_softc {
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struct wdc_softc sc_wdcdev; /* common wdc definitions */
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pci_chipset_tag_t sc_pc; /* PCI registers info */
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pcitag_t sc_tag;
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void *sc_pci_ih; /* PCI interrupt handle */
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int sc_dma_ok; /* bus-master DMA info */
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bus_space_tag_t sc_dma_iot;
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bus_space_handle_t sc_dma_ioh;
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bus_dma_tag_t sc_dmat;
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/* For AMD/nVidia */
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bus_addr_t sc_amd_regbase;
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/* For Cypress */
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const struct cy82c693_handle *sc_cy_handle;
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int sc_cy_compatchan;
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/* Vendor info (for interpreting Chip description) */
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uint32_t sc_pci_vendor;
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/* Chip description */
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const struct pciide_product_desc *sc_pp;
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/* common definitions */
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struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS];
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/* internal bookkeeping */
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struct pciide_channel { /* per-channel data */
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struct channel_softc wdc_channel; /* generic part */
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char *name;
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int hw_ok; /* hardware mapped & OK? */
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int compat; /* is it compat? */
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void *ih; /* compat or pci handle */
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bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
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/* DMA tables and DMA map for xfer, for each drive */
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struct pciide_dma_maps {
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bus_dmamap_t dmamap_table;
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struct idedma_table *dma_table;
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bus_dmamap_t dmamap_xfer;
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int dma_flags;
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} dma_maps[2];
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} pciide_channels[PCIIDE_NUM_CHANNELS];
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};
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/*
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* Functions defined by machine-dependent code.
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*/
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/* Attach compat interrupt handler, returning handle or NULL if failed. */
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#ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
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void *pciide_machdep_compat_intr_establish __P((struct device *,
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struct pci_attach_args *, int, int (*)(void *), void *));
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#endif
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