78037d3f6d
- generic soft interrupts (ie. use powerpc/softintr.c) - interrupt event counters (using the ones from powerpc/cpu.h:cpu_info where appropriate) - cleanup ibm4xx_intr.h, move implementation details to intr.c Convert all affected evbppc platforms. OK by simonb@, some points discussed with matt@
259 lines
7.8 KiB
ArmAsm
259 lines
7.8 KiB
ArmAsm
/* $NetBSD: obs200_locore.S,v 1.3 2006/06/30 17:54:50 freza Exp $ */
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/* Original Tag: locore.S,v 1.1 2003/09/23 15:21:58 shige Exp */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#undef PPC_4XX_NOCACHE
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#define _NOREGNAMES
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#include "opt_ddb.h"
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#include "opt_ipkdb.h"
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#include "opt_lockdebug.h"
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#include "opt_multiprocessor.h"
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#include "opt_ppcarch.h"
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#include "opt_ppcparam.h"
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#include "assym.h"
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#include "ksyms.h"
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#include <sys/syscall.h>
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#include <machine/param.h>
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/asm.h>
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/dcr405gp.h>
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#include <powerpc/ibm4xx/pmap.h>
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/* Function pointer for requesting board_config_data from OpenBlockS S/R BIOS */
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#define BOARD_CFG_FP (0x00100000)
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/*
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* Some instructions gas doesn't understand (yet?)
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*/
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#define bdneq bdnzf 2,
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/*
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* Globals
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*/
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GLOBAL(proc0paddr)
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.long 0 /* proc0 p_addr */
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.text
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.globl _C_LABEL(kernel_text)
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_C_LABEL(kernel_text):
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/*
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* Startup entry. Note, this must be the first thing in the text
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* segment!
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*/
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.text
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.globl __start
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__start:
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b 1f
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/* Reserve some space for info_block required for IBM eval board bootloader */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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1:
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/* Get the board_config_data from openbios */
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lis %r3,BOARD_CFG_FP@h
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ori %r3,%r3,BOARD_CFG_FP@l
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mr %r31,%r3 /* Save value in r31 */
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li %r0,0
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mtmsr %r0 /* Disable FPU/MMU/exceptions */
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isync
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/* PPC405GP errata, item #58.
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* Load string instructions may write incorrect data into the last GPR
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* targeted in the operation.
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* Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 */
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mtdcr DCR_OCM0_DSCNTL, %r0 /* Disable Data access to OCM */
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mtdcr DCR_OCM0_ISCNTL, %r0 /* Disable Instruction access to OCM. Just in case */
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/*
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* Cpu detect.
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*
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*/
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__start_cpu0:
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#ifdef PPC_4XX_NOCACHE
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/* Disable all caches for physical addresses */
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li %r0,0
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#else
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/* Allow cacheing for only the first 2GB of RAM */
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lis %r0,0xffff
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#endif
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mtdccr %r0
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mticcr %r0
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/* Invalidate all TLB entries */
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tlbia
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sync
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isync
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/* get start of bss */
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lis %r3,_C_LABEL(_edata)-4@ha
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addi %r3,%r3,_C_LABEL(_edata)-4@l
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/* get end of kernel memory */
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lis %r8,_C_LABEL(end)@ha
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addi %r8,%r8,_C_LABEL(end)@l
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/* zero bss */
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li %r4,0
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2: stwu %r4,%r4(3)
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cmpw %r3,%r8
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bne+ 2b
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#if NKSYMS || defined(DDB) || defined(LKM)
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/* If we had symbol table location we'd store it here and would've adjusted r8 here */
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lis %r7,_C_LABEL(startsym)@ha
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addi %r7,%r7,_C_LABEL(startsym)@l
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stw %r8,0(%r7)
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lis %r7,_C_LABEL(endsym)@ha
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addi %r7,%r7,_C_LABEL(endsym)@l
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stw %r8,0(%r7)
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#endif
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/*
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* Set up TLB entry to cover kernel addresses.
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*
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* XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
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* and hard hangs
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*/
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li %r0,1
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mtpid %r0
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sync
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li %r0,0
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#ifdef PPC_4XX_NOCACHE
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li %r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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li %r4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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li %r3,TLB_VALID|TLB_PG_16M
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tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
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#if 1
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/* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
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li %r0,1
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lis %r4,0x01000000@h
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ori %r3,%r4,0
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#ifdef PPC_4XX_NOCACHE
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addi %r4,%r4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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addi %r4,%r4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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addi %r3,%r3,TLB_VALID|TLB_PG_16M
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tlbwe %r4,%r0,1 /* Load the data(Low) portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag(High) portion of the entry */
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#endif
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/* set up a TLB mapping to cover uart0 */
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lis %r3,0xef000000@h /* Load the virtual address */
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ori %r4,%r3,0 /* Load the physical address */
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clrrwi %r4,%r4,10 /* Mask off the real page number */
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/* write, execute, cache inhibit, guarded */
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ori %r4,%r4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
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clrrwi %r3,%r3,10 /* Mask off the effective page number */
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ori %r3,%r3,(TLB_VALID|TLB_PG_16M)
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li %r0,2
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tlbwe %r4,%r0,1 /* Load the data portion of the entry */
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tlbwe %r3,%r0,0 /* Load the tag portion of the entry */
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/* END of TLB setup */
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INIT_CPUINFO(8,1,9,0)
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mr %r4,%r8
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lis %r3,__start@ha
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addi %r3,%r3,__start@l
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mr %r6,%r31 /* info_block address */
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bl _C_LABEL(initppc)
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bl _C_LABEL(main)
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loop: b loop /* XXX not reached */
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#include <powerpc/ibm4xx/4xx_locore.S>
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