344 lines
9.8 KiB
C
344 lines
9.8 KiB
C
/* $NetBSD: ioasic.c,v 1.37 2002/10/02 04:06:40 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Keith Bostic, Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "opt_dec_3000_300.h"
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: ioasic.c,v 1.37 2002/10/02 04:06:40 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/pte.h>
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#include <machine/rpb.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicreg.h>
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#include <dev/tc/ioasicvar.h>
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/* Definition of the driver for autoconfig. */
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int ioasicmatch __P((struct device *, struct cfdata *, void *));
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void ioasicattach __P((struct device *, struct device *, void *));
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CFATTACH_DECL(ioasic, sizeof(struct ioasic_softc),
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ioasicmatch, ioasicattach, NULL, NULL);
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int ioasic_intr __P((void *));
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int ioasic_intrnull __P((void *));
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#define C(x) ((void *)(x))
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#define IOASIC_DEV_LANCE 0
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#define IOASIC_DEV_SCC0 1
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#define IOASIC_DEV_SCC1 2
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#define IOASIC_DEV_ISDN 3
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#define IOASIC_DEV_BOGUS -1
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#define IOASIC_NCOOKIES 4
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struct ioasic_dev ioasic_devs[] = {
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{ "PMAD-BA ", IOASIC_SLOT_3_START, C(IOASIC_DEV_LANCE),
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IOASIC_INTR_LANCE, },
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{ "z8530 ", IOASIC_SLOT_4_START, C(IOASIC_DEV_SCC0),
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IOASIC_INTR_SCC_0, },
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{ "z8530 ", IOASIC_SLOT_6_START, C(IOASIC_DEV_SCC1),
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IOASIC_INTR_SCC_1, },
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{ "TOY_RTC ", IOASIC_SLOT_8_START, C(IOASIC_DEV_BOGUS),
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0, },
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{ "AMD79c30", IOASIC_SLOT_9_START, C(IOASIC_DEV_ISDN),
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IOASIC_INTR_ISDN_TXLOAD | IOASIC_INTR_ISDN_RXLOAD, },
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};
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int ioasic_ndevs = sizeof(ioasic_devs) / sizeof(ioasic_devs[0]);
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struct ioasicintr {
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int (*iai_func) __P((void *));
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void *iai_arg;
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struct evcnt iai_evcnt;
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} ioasicintrs[IOASIC_NCOOKIES];
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tc_addr_t ioasic_base; /* XXX XXX XXX */
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/* There can be only one. */
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int ioasicfound;
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int
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ioasicmatch(parent, cfdata, aux)
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struct device *parent;
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struct cfdata *cfdata;
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void *aux;
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{
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struct tc_attach_args *ta = aux;
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/* Make sure that we're looking for this type of device. */
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if (strncmp("FLAMG-IO", ta->ta_modname, TC_ROM_LLEN))
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return (0);
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/* Check that it can actually exist. */
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if ((cputype != ST_DEC_3000_500) && (cputype != ST_DEC_3000_300))
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panic("ioasicmatch: how did we get here?");
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if (ioasicfound)
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return (0);
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return (1);
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}
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void
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ioasicattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct ioasic_softc *sc = (struct ioasic_softc *)self;
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struct tc_attach_args *ta = aux;
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#ifdef DEC_3000_300
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u_long ssr;
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#endif
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u_long i, imsk;
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const struct evcnt *pevcnt;
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char *cp;
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ioasicfound = 1;
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sc->sc_bst = ta->ta_memt;
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if (bus_space_map(ta->ta_memt, ta->ta_addr,
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0x400000, 0, &sc->sc_bsh)) {
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printf("%s: unable to map device\n", sc->sc_dv.dv_xname);
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return;
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}
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sc->sc_dmat = ta->ta_dmat;
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ioasic_base = sc->sc_base = ta->ta_addr; /* XXX XXX XXX */
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#ifdef DEC_3000_300
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if (cputype == ST_DEC_3000_300) {
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ssr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR);
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ssr |= IOASIC_CSR_FASTMODE;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_CSR, ssr);
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printf(": slow mode\n");
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} else
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#endif
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printf(": fast mode\n");
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/*
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* Turn off all device interrupt bits.
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* (This does _not_ include 3000/300 TC option slot bits.
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*/
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imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
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for (i = 0; i < ioasic_ndevs; i++)
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imsk &= ~ioasic_devs[i].iad_intrbits;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
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/*
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* Set up interrupt handlers.
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*/
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pevcnt = tc_intr_evcnt(parent, ta->ta_cookie);
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for (i = 0; i < IOASIC_NCOOKIES; i++) {
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ioasicintrs[i].iai_func = ioasic_intrnull;
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ioasicintrs[i].iai_arg = (void *)i;
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cp = malloc(12, M_DEVBUF, M_NOWAIT);
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if (cp == NULL)
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panic("ioasicattach");
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sprintf(cp, "slot %lu", i);
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evcnt_attach_dynamic(&ioasicintrs[i].iai_evcnt,
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EVCNT_TYPE_INTR, pevcnt, self->dv_xname, cp);
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}
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tc_intr_establish(parent, ta->ta_cookie, TC_IPL_NONE, ioasic_intr, sc);
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/*
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* Try to configure each device.
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*/
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ioasic_attach_devs(sc, ioasic_devs, ioasic_ndevs);
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}
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void
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ioasic_intr_establish(ioa, cookie, level, func, arg)
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struct device *ioa;
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void *cookie, *arg;
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tc_intrlevel_t level;
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int (*func) __P((void *));
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{
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struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0];
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u_long dev, i, imsk;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func != ioasic_intrnull)
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panic("ioasic_intr_establish: cookie %lu twice", dev);
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ioasicintrs[dev].iai_func = func;
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ioasicintrs[dev].iai_arg = arg;
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_establish: invalid cookie.");
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imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
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imsk |= ioasic_devs[i].iad_intrbits;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
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}
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void
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ioasic_intr_disestablish(ioa, cookie)
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struct device *ioa;
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void *cookie;
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{
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struct ioasic_softc *sc = (void *)ioasic_cd.cd_devs[0];
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u_long dev, i, imsk;
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dev = (u_long)cookie;
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#ifdef DIAGNOSTIC
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/* XXX check cookie. */
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#endif
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if (ioasicintrs[dev].iai_func == ioasic_intrnull)
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panic("ioasic_intr_disestablish: cookie %lu missing intr", dev);
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/* Enable interrupts for the device. */
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for (i = 0; i < ioasic_ndevs; i++)
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if (ioasic_devs[i].iad_cookie == cookie)
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break;
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if (i == ioasic_ndevs)
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panic("ioasic_intr_disestablish: invalid cookie.");
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imsk = bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK);
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imsk &= ~ioasic_devs[i].iad_intrbits;
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, IOASIC_IMSK, imsk);
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ioasicintrs[dev].iai_func = ioasic_intrnull;
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ioasicintrs[dev].iai_arg = (void *)dev;
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}
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int
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ioasic_intrnull(val)
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void *val;
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{
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panic("ioasic_intrnull: uncaught IOASIC intr for cookie %ld",
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(u_long)val);
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}
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/*
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* ASIC interrupt handler.
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*/
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int
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ioasic_intr(val)
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void *val;
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{
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register struct ioasic_softc *sc = val;
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register int ifound;
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int gifound;
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u_int32_t sir, osir;
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gifound = 0;
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do {
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ifound = 0;
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tc_syncbus();
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osir = sir =
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, IOASIC_INTR);
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#define INCRINTRCNT(slot) ioasicintrs[slot].iai_evcnt.ev_count++
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/* XXX DUPLICATION OF INTERRUPT BIT INFORMATION... */
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#define CHECKINTR(slot, bits, clear) \
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if (sir & (bits)) { \
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ifound = 1; \
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INCRINTRCNT(slot); \
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(*ioasicintrs[slot].iai_func) \
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(ioasicintrs[slot].iai_arg); \
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if (clear) \
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sir &= ~(bits); \
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}
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CHECKINTR(IOASIC_DEV_SCC0, IOASIC_INTR_SCC_0, 0);
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CHECKINTR(IOASIC_DEV_SCC1, IOASIC_INTR_SCC_1, 0);
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CHECKINTR(IOASIC_DEV_LANCE, IOASIC_INTR_LANCE, 0);
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CHECKINTR(IOASIC_DEV_ISDN, IOASIC_INTR_ISDN_TXLOAD |
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IOASIC_INTR_ISDN_RXLOAD | IOASIC_INTR_ISDN_OVRUN, 1);
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if (sir != osir)
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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IOASIC_INTR, sir);
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gifound |= ifound;
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} while (ifound);
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return (gifound);
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}
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