163 lines
6.9 KiB
C
163 lines
6.9 KiB
C
/* $NetBSD: gtsdmareg.h,v 1.2 2003/11/02 10:31:06 wiz Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* gtsdmareg.h - register defines for GT-64260 SDMA
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*
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* creation Sun Apr 8 20:22:51 PDT 2001 cliff
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*/
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#ifndef _GTSDMAREG_H
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#define _GTSDMAREG_H
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#ifndef BIT
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#define BIT(bitno) (1U << (bitno))
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#endif
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#ifndef BITS
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#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
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#endif
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/*******************************************************************************
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*
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* SDMA register address offsets relative to the base mapping
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*/
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#define SDMA_SDC0 0x4000 /* SDMA #0 Configuration Register */
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#define SDMA_SDCM0 0x4008 /* SDMA #0 Command Register */
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#define SDMA_SCRDP0 0x4810 /* SDMA #0 Current RX Desc. Pointer */
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#define SDMA_SCTDP0 0x4c10 /* SDMA #0 Current TX Desc. Pointer */
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#define SDMA_SFTDP0 0x4c14 /* SDMA #0 First TX Desc. Pointer */
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#define SDMA_SDC1 0x6000 /* SDMA #1 Configuration Register */
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#define SDMA_SDCM1 0x6008 /* SDMA #1 Command Register */
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#define SDMA_SCRDP1 0x6810 /* SDMA #1 Current RX Desc. Pointer */
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#define SDMA_SCTDP1 0x6c10 /* SDMA #1 Current TX Desc. Pointer */
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#define SDMA_SFTDP1 0x6c14 /* SDMA #1 First TX Desc. Pointer */
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#define SDMA_ICAUSE 0xb800 /* Interrupt Cause Register */
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#define SDMA_IMASK 0xb880 /* Interrupt Mask Register */
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#define SDMA_U_SDC(u) (SDMA_SDC0 + (((u) & 1) << 13))
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#define SDMA_U_SDCM(u) (SDMA_SDCM0 + (((u) & 1) << 13))
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#define SDMA_U_SCRDP(u) (SDMA_SCRDP0 + (((u) & 1) << 13))
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#define SDMA_U_SCTDP(u) (SDMA_SCTDP0 + (((u) & 1) << 13))
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#define SDMA_U_SFTDP(u) (SDMA_SFTDP0 + (((u) & 1) << 13))
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/*******************************************************************************
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*
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* SDMA register values and bit definitions
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*/
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/*
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* SDMA Configuration Register
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*/
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#define SDMA_SDC_RFT BIT(0) /* RX FIFO Threshold */
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#define SDMA_SDC_SFM BIT(1) /* Single Frame Mode */
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#define SDMA_SDC_RC_MASK BITS(5,2) /* Re-TX count */
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#define SDMA_SDC_RC_SHIFT 2
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#define SDMA_SDC_BLMR BIT(6) /* RX Big=0 Lil=1 Endian mode */
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#define SDMA_SDC_BLMT BIT(7) /* TX Big=0 Lil=1 Endian mode */
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#define SDMA_SDC_POVR BIT(8) /* PCI Override */
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#define SDMA_SDC_RIFB BIT(9) /* RX Intr on Frame boundaries */
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#define SDMA_SDC_RESa BITS(11,10)
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#define SDMA_SDC_BSZ_MASK BITS(13,12) /* Maximum Burst Size */
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#define SDMA_SDC_BSZ_1x64 (0 << 12) /* 1 64 bit word */
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#define SDMA_SDC_BSZ_2x64 (1 << 12) /* 2 64 bit words */
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#define SDMA_SDC_BSZ_4x64 (2 << 12) /* 4 64 bit words */
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#define SDMA_SDC_BSZ_8x64 (3 << 12) /* 8 64 bit words */
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#define SDMA_SDC_RESb BITS(31,14)
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#define SDMA_SDC_RES (SDMA_SDC_RESa|SDMA_SDC_RESb)
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/*
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* SDMA Command Register
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*/
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#define SDMA_SDCM_RESa BITS(6,0)
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#define SDMA_SDCM_ERD BIT(7) /* Enable RX DMA */
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#define SDMA_SDCM_RESb BITS(14,8)
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#define SDMA_SDCM_AR BIT(15) /* Abort Receive */
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#define SDMA_SDCM_STD BIT(16) /* Stop TX */
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#define SDMA_SDCM_RESc BITS(22,17)
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#define SDMA_SDCM_TXD BIT(23) /* TX Demand */
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#define SDMA_SDCM_RESd BITS(30,24)
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#define SDMA_SDCM_AT BIT(31) /* Abort TX */
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#define SDMA_SDCM_RES \
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(SDMA_SDCM_RESa|SDMA_SDCM_RESb|SDMA_SDCM_RESc|SDMA_SDCM_RESd)
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/*
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* SDMA Interrupt Cause and Mask Register bits
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*/
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#define U__(bits,u) ((bits) << (((u) % 2) * 8))
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#define SDMA_INTR_RXBUF(u) U__(BIT(0),u) /* SDMA #0 Rx Buffer Return */
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#define SDMA_INTR_RXERR(u) U__(BIT(1),u) /* SDMA #0 Rx Error */
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#define SDMA_INTR_TXBUF(u) U__(BIT(2),u) /* SDMA #0 Tx Buffer Return */
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#define SDMA_INTR_TXEND(u) U__(BIT(3),u) /* SDMA #0 Tx End */
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#define SDMA_INTR_RESa BITS(7,4)
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#define SDMA_INTR_RESb BITS(31,12)
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#define SDMA_INTR_RES (SDMA_INTR_RESa|SDMA_INTR_RESb)
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#define SDMA_U_INTR_MASK(u) U__(BITS(3,0),u)
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/*******************************************************************************
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*
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* SDMA descriptor structure and definitions
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*/
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/*
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* SDMA descriptor structure used for both TX and RX
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* the `sdma_csr' and `sdma_cnt' fields differ for RX and TX
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* `sdma_csr' varies depending on how it is tasked;
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* see "gtmpscreg.h" for defines on SDMA descriptor CSR values
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* for MPSC UART mode. Note that pointer fields are physical addrs.
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*/
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typedef struct sdma_desc {
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u_int32_t sdma_cnt; /* size (rx) or shadow (tx) and count */
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u_int32_t sdma_csr; /* command/status */
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u_int32_t sdma_next; /* next descriptor link */
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u_int32_t sdma_bufp; /* buffer pointer */
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} sdma_desc_t;
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#define SDMA_RX_CNT_BCNT_SHIFT 0 /* byte count */
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#define SDMA_RX_CNT_BCNT_MASK BITS(15,0) /* " " */
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#define SDMA_RX_CNT_BUFSZ_SHIFT 16 /* buffer size */
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#define SDMA_RX_CNT_BUFSZNT_SIZE_MASK BITS(31,19) /* " " */
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#define SDMA_RX_CNT_BUFP_MASK BITS(31,3) /* buffer pointer */
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#define SDMA_RX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */
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#define SDMA_TX_CNT_SBC_SHIFT 0 /* shadow byte count */
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#define SDMA_TX_CNT_SBC_MASK BITS(15,0) /* " " " */
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#define SDMA_TX_CNT_BCNT_SHIFT 16 /* byte count */
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#define SDMA_TX_CNT_BCNT_MASK BITS(31,16 /* " " */
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#define SDMA_TX_CNT_NEXT_MASK BITS(31,4) /* next desc. pointer */
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#endif /* _GTSDMAREG_H */
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