e345f0f17c
out from UCHIYAMA Yasushi's PCI BIOS patches, and fairly heavily reworked by me. Main differences: - Only use the PCI BIOS to get the config mechanism and interrupt routing info for now. No need to use the BIOS for PCI config access right now, since the old mechanism works fine, and this keeps the code smaller. - PCI BIOS initialization code path is much different. - Always use the $PIR table if it exists, and only fallback to the PCI BIOS 2.1 GetInterruptRouting call if it's not there. This module does not include any of the fixup code; that is coming in separate commits.
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/* $NetBSD: pcibios.h,v 1.1 1999/11/17 01:16:37 thorpej Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Data structure definitions for the PCI BIOS interface.
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*/
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/*
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* PCI BIOS return codes.
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*/
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#define PCIBIOS_SUCCESS 0x00
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#define PCIBIOS_SERVICE_NOT_PRESENT 0x80
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#define PCIBIOS_FUNCTION_NOT_SUPPORTED 0x81
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#define PCIBIOS_BAD_VENDOR_ID 0x83
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#define PCIBIOS_DEVICE_NOT_FOUND 0x86
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#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
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#define PCIBIOS_SET_FAILED 0x88
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#define PCIBIOS_BUFFER_TOO_SMALL 0x89
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/*
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* PCI IRQ Routing Table definitions.
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*/
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/*
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* Slot entry (per PCI 2.1)
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*/
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struct pcibios_linkmap {
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u_int8_t link;
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u_int16_t bitmap;
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} __attribute__((__packed__));
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struct pcibios_intr_routing {
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u_int8_t bus;
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u_int8_t device;
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struct pcibios_linkmap linkmap[4]; /* INT[A:D]# */
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u_int8_t slot;
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u_int8_t reserved;
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} __attribute__((__packed__));
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/*
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* $PIR header. Reference:
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*
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* http://www.microsoft.com/HWDEV/busbios/PCIIRQ.htm
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*/
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struct pcibios_pir_header {
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u_int32_t signature; /* $PIR */
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u_int16_t version;
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u_int16_t tablesize;
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u_int8_t router_bus;
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u_int8_t router_devfunc;
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u_int16_t exclusive_irq;
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u_int32_t compat_router; /* PCI vendor/product */
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u_int32_t miniport;
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u_int8_t reserved[11];
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u_int8_t checksum;
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} __attribute__((__packed__));
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void pcibios_init __P((void));
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extern struct pcibios_pir_header pcibios_pir_header;
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extern struct pcibios_intr_routing *pcibios_pir_table;
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extern int pcibios_pir_table_nentries;
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extern int pcibios_max_bus;
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