2c7e45820a
requires us to configure the IOPLUS to use the appropriate DMA channel, depending on what other expansion cards may be installed. Further, we need to do a bit more configuration of the sq(4) DMA engine, which apparently was formerly being configured properly by the PROM. Use the same values, which appear to work fine. Also, extend the gio_arb_config interface as needed. NB: We're currently setting the IOPLUS board to long burst, but it may be better to use realtime. This will require some experimentation.
448 lines
12 KiB
C
448 lines
12 KiB
C
/* $NetBSD: imc.c,v 1.28 2007/02/19 20:14:30 rumble Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.28 2007/02/19 20:14:30 rumble Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/locore.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/machtype.h>
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#include <machine/sysconf.h>
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#include <sgimips/dev/imcreg.h>
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#include <sgimips/dev/imcvar.h>
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#include <sgimips/gio/giovar.h>
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#include "locators.h"
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struct imc_softc {
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struct device sc_dev;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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int eisa_present;
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};
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static int imc_match(struct device *, struct cfdata *, void *);
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static void imc_attach(struct device *, struct device *, void *);
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static int imc_print(void *, const char *);
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static void imc_bus_reset(void);
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static void imc_bus_error(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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static void imc_watchdog_reset(void);
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static void imc_watchdog_disable(void);
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static void imc_watchdog_enable(void);
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CFATTACH_DECL(imc, sizeof(struct imc_softc),
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imc_match, imc_attach, NULL, NULL);
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struct imc_attach_args {
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const char* iaa_name;
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bus_space_tag_t iaa_st;
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bus_space_handle_t iaa_sh;
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/* ? */
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long iaa_offset;
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int iaa_intr;
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#if 0
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int iaa_stride;
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#endif
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};
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int imc_gio64_arb_config(int, uint32_t);
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struct imc_softc isc;
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static int
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imc_match(struct device *parent, struct cfdata *match, void *aux)
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{
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if ( (mach_type == MACH_SGI_IP22) || (mach_type == MACH_SGI_IP20) )
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return (1);
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return (0);
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}
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static void
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imc_attach(struct device *parent, struct device *self, void *aux)
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{
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u_int32_t reg;
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struct imc_attach_args iaa;
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struct mainbus_attach_args *ma = aux;
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u_int32_t sysid;
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isc.iot = SGIMIPS_BUS_SPACE_HPC;
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if (bus_space_map(isc.iot, ma->ma_addr, 0,
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BUS_SPACE_MAP_LINEAR, &isc.ioh))
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panic("imc_attach: could not allocate memory\n");
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platform.bus_reset = imc_bus_reset;
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platform.watchdog_reset = imc_watchdog_reset;
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platform.watchdog_disable = imc_watchdog_disable;
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platform.watchdog_enable = imc_watchdog_enable;
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sysid = bus_space_read_4(isc.iot, isc.ioh, IMC_SYSID);
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/* EISA exists on IP22 only */
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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isc.eisa_present = (sysid & IMC_SYSID_HAVEISA);
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else
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isc.eisa_present = 0;
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printf(": revision %d", (sysid & IMC_SYSID_REVMASK));
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if (isc.eisa_present)
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printf(", EISA bus present");
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printf("\n");
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/* Clear CPU/GIO error status registers to clear any leftover bits. */
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imc_bus_reset();
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/* Hook the bus error handler into the ISR */
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platform.intr4 = imc_bus_error;
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/*
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* Enable parity reporting on GIO/main memory transactions.
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* Disable parity checking on CPU bus transactions (as turning
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* it on seems to cause spurious bus errors), but enable parity
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* checking on CPU reads from main memory (note that this bit
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* has the opposite sense... Turning it on turns the checks off!).
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* Finally, turn on interrupt writes to the CPU from the MC.
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*/
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
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reg |= (IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR | IMC_CPUCTRL0_INTENA);
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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/* Setup the MC write buffer depth */
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL1);
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reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13;
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/*
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* Force endianness on the onboard HPC and both slots.
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* This should be safe for Fullhouse, but leave it conditional
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* for now.
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*/
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if (mach_type == MACH_SGI_IP20 || (mach_type == MACH_SGI_IP22 &&
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mach_subtype == MACH_SGI_IP22_GUINNESS)) {
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reg |= IMC_CPUCTRL1_HPCFX;
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reg |= IMC_CPUCTRL1_EXP0FX;
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reg |= IMC_CPUCTRL1_EXP1FX;
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reg &= ~IMC_CPUCTRL1_HPCLITTLE;
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reg &= ~IMC_CPUCTRL1_EXP0LITTLE;
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reg &= ~IMC_CPUCTRL1_EXP1LITTLE;
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}
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL1, reg);
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/*
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* Set GIO64 arbitrator configuration register:
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*
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* Preserve PROM-set graphics-related bits, as they seem to depend
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* on the graphics variant present and I'm not sure how to figure
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* that out or 100% sure what the correct settings are for each.
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*/
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);
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reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST);
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/* Rest of settings are machine/board dependant */
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if (mach_type == MACH_SGI_IP20)
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{
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reg |= IMC_GIO64ARB_ONEGIO;
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reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);
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reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);
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reg &= ~(IMC_GIO64ARB_HPC64 |
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IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EISA64 |
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IMC_GIO64ARB_EXP064 | IMC_GIO64ARB_EXP164 |
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IMC_GIO64ARB_EXP0PIPE | IMC_GIO64ARB_EXP1PIPE);
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}
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else
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{
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/*
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* GIO64 invariant for all IP22 platforms: one GIO bus,
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* HPC1 @ 64
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*/
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reg |= IMC_GIO64ARB_ONEGIO | IMC_GIO64ARB_HPC64;
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switch (mach_subtype) {
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case MACH_SGI_IP22_GUINNESS:
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/* XXX is MST mutually exclusive? */
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reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);
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reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);
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/* EISA can bus-master, is 64-bit */
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reg |= (IMC_GIO64ARB_EISAMST | IMC_GIO64ARB_EISA64);
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break;
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case MACH_SGI_IP22_FULLHOUSE:
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/*
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* All Fullhouse boards have a 64-bit HPC2 and pipelined
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* EXP0 slot.
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*/
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reg |= (IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EXP0PIPE);
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if (mach_boardrev < 2) {
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/* EXP0 realtime, EXP1 can master */
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reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1MST);
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} else {
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/* EXP1 pipelined as well, EISA masters */
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reg |= (IMC_GIO64ARB_EXP1PIPE | IMC_GIO64ARB_EISAMST);
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}
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break;
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}
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}
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);
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if (isc.eisa_present) {
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#if notyet
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memset(&iaa, 0, sizeof(iaa));
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config_found_ia(self, "eisabus", (void*)&iaa, eisabusprint);
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#endif
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}
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memset(&iaa, 0, sizeof(iaa));
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config_found_ia(self, "giobus", (void*)&iaa, imc_print);
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imc_watchdog_enable();
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}
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static int
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imc_print(void *aux, const char *name)
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{
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if (name)
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aprint_normal("gio at %s", name);
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return UNCONF;
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}
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static void
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imc_bus_reset(void)
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{
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT, 0);
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT, 0);
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}
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static void
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imc_bus_error(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
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{
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printf("bus error: cpu_stat %08x addr %08x, gio_stat %08x addr %08x\n",
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bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT),
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bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRADDR),
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bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT),
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bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRADDR) );
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imc_bus_reset();
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}
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static void
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imc_watchdog_reset(void)
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{
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bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
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}
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static void
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imc_watchdog_disable(void)
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{
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u_int32_t reg;
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bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg &= ~(IMC_CPUCTRL0_WDOG);
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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}
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static void
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imc_watchdog_enable(void)
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{
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u_int32_t reg;
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/* enable watchdog and clear it */
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg |= IMC_CPUCTRL0_WDOG;
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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imc_watchdog_reset();
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}
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/* intended to be called from gio/gio.c only */
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int
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imc_gio64_arb_config(int slot, uint32_t flags)
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{
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uint32_t reg;
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/* GIO_SLOT_EXP1 is unusable on Fullhouse */
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if (slot == GIO_SLOT_EXP1 && mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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return (EINVAL);
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/* GIO_SLOT_GFX is only usable on Fullhouse */
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if (slot == GIO_SLOT_GFX && mach_subtype != MACH_SGI_IP22_FULLHOUSE)
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return (EINVAL);
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/* GIO_SLOT_GFX is always pipelined */
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if (slot == GIO_SLOT_GFX && (flags & GIO_ARB_NOPIPE))
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return (EINVAL);
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/* IP20 does not support pipelining (XXX what about Indy?) */
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if (((flags & GIO_ARB_PIPE) || (flags & GIO_ARB_NOPIPE)) &&
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mach_type == MACH_SGI_IP20)
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return (EINVAL);
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);
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if (flags & GIO_ARB_RT) {
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if (slot == GIO_SLOT_EXP0)
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reg |= IMC_GIO64ARB_EXP0RT;
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else if (slot == GIO_SLOT_EXP1)
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reg |= IMC_GIO64ARB_EXP1RT;
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else if (slot == GIO_SLOT_GFX)
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reg |= IMC_GIO64ARB_GRXRT;
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}
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if (flags & GIO_ARB_MST) {
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if (slot == GIO_SLOT_EXP0)
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reg |= IMC_GIO64ARB_EXP0MST;
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else if (slot == GIO_SLOT_EXP1)
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reg |= IMC_GIO64ARB_EXP1MST;
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else if (slot == GIO_SLOT_GFX)
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reg |= IMC_GIO64ARB_GRXMST;
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}
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if (flags & GIO_ARB_PIPE) {
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if (slot == GIO_SLOT_EXP0)
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reg |= IMC_GIO64ARB_EXP0PIPE;
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else if (slot == GIO_SLOT_EXP1)
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reg |= IMC_GIO64ARB_EXP1PIPE;
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}
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if (flags & GIO_ARB_LB) {
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if (slot == GIO_SLOT_EXP0)
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reg &= ~IMC_GIO64ARB_EXP0RT;
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else if (slot == GIO_SLOT_EXP1)
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reg &= ~IMC_GIO64ARB_EXP1RT;
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else if (slot == GIO_SLOT_GFX)
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reg &= ~IMC_GIO64ARB_GRXRT;
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}
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if (flags & GIO_ARB_SLV) {
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if (slot == GIO_SLOT_EXP0)
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reg &= ~IMC_GIO64ARB_EXP0MST;
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else if (slot == GIO_SLOT_EXP1)
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reg &= ~IMC_GIO64ARB_EXP1MST;
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else if (slot == GIO_SLOT_GFX)
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reg &= ~IMC_GIO64ARB_GRXMST;
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}
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if (flags & GIO_ARB_NOPIPE) {
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if (slot == GIO_SLOT_EXP0)
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reg &= ~IMC_GIO64ARB_EXP0PIPE;
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else if (slot == GIO_SLOT_EXP1)
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reg &= ~IMC_GIO64ARB_EXP1PIPE;
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}
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if (flags & GIO_ARB_32BIT) {
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if (slot == GIO_SLOT_EXP0)
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reg &= ~IMC_GIO64ARB_EXP064;
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else if (slot == GIO_SLOT_EXP1)
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reg &= ~IMC_GIO64ARB_EXP164;
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}
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if (flags & GIO_ARB_64BIT) {
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if (slot == GIO_SLOT_EXP0)
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reg |= IMC_GIO64ARB_EXP064;
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else if (slot == GIO_SLOT_EXP1)
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reg |= IMC_GIO64ARB_EXP164;
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}
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if (flags & GIO_ARB_HPC2_32BIT)
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reg &= ~IMC_GIO64ARB_HPCEXP64;
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if (flags & GIO_ARB_HPC2_64BIT)
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reg |= IMC_GIO64ARB_HPCEXP64;
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bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);
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return (0);
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}
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/*
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* According to chapter 19 of the "IRIX Device Driver Programmer's Guide",
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* some GIO devices, which do not drive all data lines, may cause false
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* memory read parity errors on the SysAD bus. The workaround is to disable
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* parity checking.
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*/
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void
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imc_disable_sysad_parity()
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{
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uint32_t reg;
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if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
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return;
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg |= IMC_CPUCTRL0_NCHKMEMPAR;
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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}
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void
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imc_enable_sysad_parity()
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{
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uint32_t reg;
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if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
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return;
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
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bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
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}
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int
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imc_is_sysad_parity_enabled()
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{
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uint32_t reg;
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if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
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return (0);
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reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
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return (reg & IMC_CPUCTRL0_NCHKMEMPAR);
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}
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