274 lines
10 KiB
C
274 lines
10 KiB
C
/* $NetBSD: cache.h,v 1.20 1998/10/09 10:48:14 pk Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cache.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef SPARC_CACHE_H
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#define SPARC_CACHE_H
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/*
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* Sun-4 and Sun-4c virtual address cache.
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*
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* Sun-4 virtual caches come in two flavors, write-through (Sun-4c)
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* and write-back (Sun-4). The write-back caches are much faster
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* but require a bit more care.
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*
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*/
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enum vactype { VAC_UNKNOWN, VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK };
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/*
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* Cache tags can be written in control space, and must be set to 0
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* (or invalid anyway) before turning on the cache. The tags are
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* addressed as an array of 32-bit structures of the form:
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*
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* struct cache_tag {
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* u_int :7, (unused; must be zero)
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* ct_cid:3, (context ID)
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* ct_w:1, (write flag from PTE)
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* ct_s:1, (supervisor flag from PTE)
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* ct_v:1, (set => cache entry is valid)
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* :3, (unused; must be zero)
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* ct_tid:14, (cache tag ID)
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* :2; (unused; must be zero)
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* };
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*
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* The SPARCstation 1 cache sees virtual addresses as:
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*
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* struct cache_va {
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* u_int :2, (unused; probably copies of va_tid<13>)
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* cva_tid:14, (tag ID)
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* cva_line:12, (cache line number)
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* cva_byte:4; (byte in cache line)
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* };
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*
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* (The SS2 cache is similar but has half as many lines, each twice as long.)
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*
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* Note that, because the 12-bit line ID is `wider' than the page offset,
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* it is possible to have one page map to two different cache lines.
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* This can happen whenever two different physical pages have the same bits
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* in the part of the virtual address that overlaps the cache line ID, i.e.,
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* bits <15:12>. In order to prevent cache duplication, we have to
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* make sure that no one page has more than one virtual address where
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* (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v
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* when a cache miss occurs on a write, i.e., if va1 is in the cache and
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* va2 is not, and you write to va2, va1 goes out of the cache. If va1
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* is in the cache and va2 is not, reading va2 also causes va1 to become
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* uncached, and the [same] data is then read from main memory into the
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* cache.)
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*
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* The other alternative, of course, is to disable caching of aliased
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* pages. (In a few cases this might be faster anyway, but we do it
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* only when forced.)
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*
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* The Sun4, since it has an 8K pagesize instead of 4K, needs to check
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* bits that are one position higher.
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*/
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/* Some more well-known values: */
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#define CACHE_ALIAS_DIST_SUN4 0x20000
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#define CACHE_ALIAS_DIST_SUN4C 0x10000
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#define CACHE_ALIAS_BITS_SUN4 0x1e000
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#define CACHE_ALIAS_BITS_SUN4C 0xf000
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#define CACHE_ALIAS_DIST_HS128k 0x20000
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#define CACHE_ALIAS_BITS_HS128k 0x1f000
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#define CACHE_ALIAS_DIST_HS256k 0x40000
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#define CACHE_ALIAS_BITS_HS256k 0x3f000
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/*
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* Assuming a tag format where the least significant bits are the byte offset
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* into the cache line, and the next-most significant bits are the line id,
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* we can calculate the appropriate aliasing constants. We also assume that
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* the linesize and total cache size are powers of 2.
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*/
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#define GUESS_CACHE_ALIAS_BITS ((cpuinfo.cacheinfo.c_totalsize - 1) & ~PGOFSET)
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#define GUESS_CACHE_ALIAS_DIST (cpuinfo.cacheinfo.c_totalsize)
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extern int cache_alias_dist; /* */
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extern int cache_alias_bits;
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/* Optimize cache alias macros on single architecture kernels */
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#if defined(SUN4) && !defined(SUN4C) && !defined(SUN4M)
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#define CACHE_ALIAS_DIST CACHE_ALIAS_DIST_SUN4
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#define CACHE_ALIAS_BITS CACHE_ALIAS_BITS_SUN4
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#elif !defined(SUN4) && defined(SUN4C) && !defined(SUN4M)
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#define CACHE_ALIAS_DIST CACHE_ALIAS_DIST_SUN4C
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#define CACHE_ALIAS_BITS CACHE_ALIAS_BITS_SUN4C
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#else
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#define CACHE_ALIAS_DIST cache_alias_dist
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#define CACHE_ALIAS_BITS cache_alias_bits
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#endif
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/*
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* True iff a1 and a2 are `bad' aliases (will cause cache duplication).
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*/
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#define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & CACHE_ALIAS_BITS)
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/*
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* Routines for dealing with the cache.
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*/
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void sun4_cache_enable __P((void)); /* turn it on */
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void ms1_cache_enable __P((void)); /* turn it on */
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void viking_cache_enable __P((void)); /* turn it on */
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void hypersparc_cache_enable __P((void)); /* turn it on */
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void swift_cache_enable __P((void)); /* turn it on */
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void cypress_cache_enable __P((void)); /* turn it on */
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void turbosparc_cache_enable __P((void)); /* turn it on */
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void sun4_vcache_flush_context __P((void)); /* flush current context */
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void sun4_vcache_flush_region __P((int)); /* flush region in cur ctx */
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void sun4_vcache_flush_segment __P((int, int));/* flush seg in cur ctx */
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void sun4_vcache_flush_page __P((int va)); /* flush page in cur ctx */
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void sun4_cache_flush __P((caddr_t, u_int));/* flush region */
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void srmmu_vcache_flush_context __P((void)); /* flush current context */
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void srmmu_vcache_flush_region __P((int)); /* flush region in cur ctx */
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void srmmu_vcache_flush_segment __P((int, int));/* flush seg in cur ctx */
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void srmmu_vcache_flush_page __P((int va)); /* flush page in cur ctx */
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void srmmu_cache_flush __P((caddr_t, u_int));/* flush region */
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void ms1_cache_flush __P((caddr_t, u_int));
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void viking_cache_flush __P((caddr_t, u_int));
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void viking_pcache_flush_line __P((int, int));
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void srmmu_pcache_flush_line __P((int, int));
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void hypersparc_pure_vcache_flush __P((void));
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void ms1_cache_flush_all __P((void));
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void srmmu_cache_flush_all __P((void));
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void cypress_cache_flush_all __P((void));
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void hypersparc_cache_flush_all __P((void));
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extern void sparc_noop __P((void));
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#define noop_vcache_flush_context \
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(void (*)__P((void))) sparc_noop
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#define noop_vcache_flush_region \
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(void (*)__P((int))) sparc_noop
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#define noop_vcache_flush_segment \
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(void (*)__P((int,int))) sparc_noop
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#define noop_vcache_flush_page \
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(void (*)__P((int))) sparc_noop
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#define noop_cache_flush \
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(void (*)__P((caddr_t, u_int))) sparc_noop
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#define noop_pcache_flush_line \
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(void (*)__P((int, int))) sparc_noop
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#define noop_pure_vcache_flush \
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(void (*)__P((void))) sparc_noop
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#define noop_cache_flush_all \
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(void (*)__P((void))) sparc_noop
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/*
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* The SMP versions of the cache flush functions. These functions
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* send a "cache flush" message to each processor.
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*/
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void smp_vcache_flush_context __P((void)); /* flush current context */
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void smp_vcache_flush_region __P((int)); /* flush region in cur ctx */
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void smp_vcache_flush_segment __P((int, int));/* flush seg in cur ctx */
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void smp_vcache_flush_page __P((int va)); /* flush page in cur ctx */
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void smp_cache_flush __P((caddr_t, u_int)); /* flush region */
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#define cache_flush_page(va) cpuinfo.vcache_flush_page(va)
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#define cache_flush_segment(vr,vs) cpuinfo.vcache_flush_segment(vr,vs)
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#define cache_flush_region(vr) cpuinfo.vcache_flush_region(vr)
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#define cache_flush_context() cpuinfo.vcache_flush_context()
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/*
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* Cache control information.
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*/
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struct cacheinfo {
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int c_totalsize; /* total size, in bytes */
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/* if split, MAX(icache,dcache) */
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int c_enabled; /* true => cache is enabled */
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int c_hwflush; /* true => have hardware flush */
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int c_linesize; /* line size, in bytes */
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int c_l2linesize; /* log2(linesize) */
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int c_nlines; /* number of cache lines */
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int c_physical; /* true => cache has physical
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address tags */
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int c_associativity; /* # of "buckets" in cache line */
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int c_split; /* true => cache is split */
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int ic_totalsize; /* instruction cache */
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int ic_enabled;
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int ic_linesize;
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int ic_l2linesize;
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int ic_nlines;
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int ic_associativity;
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int dc_totalsize; /* data cache */
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int dc_enabled;
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int dc_linesize;
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int dc_l2linesize;
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int dc_nlines;
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int dc_associativity;
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int ec_totalsize; /* external cache info */
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int ec_enabled;
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int ec_linesize;
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int ec_l2linesize;
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int ec_nlines;
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int ec_associativity;
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enum vactype c_vactype;
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};
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#define CACHEINFO cpuinfo.cacheinfo
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/*
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* Cache control statistics.
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*/
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struct cachestats {
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int cs_npgflush; /* # page flushes */
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int cs_nsgflush; /* # seg flushes */
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int cs_nrgflush; /* # seg flushes */
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int cs_ncxflush; /* # context flushes */
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int cs_nraflush; /* # range flushes */
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#ifdef notyet
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int cs_ra[65]; /* pages/range */
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#endif
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};
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#endif /* SPARC_CACHE_H */
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