172 lines
4.9 KiB
C
172 lines
4.9 KiB
C
/* $NetBSD: pci_bus_fixup.c,v 1.4 2002/01/22 15:08:53 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PCI bus renumbering support.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_bus_fixup.c,v 1.4 2002/01/22 15:08:53 uch Exp $");
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#include "opt_pcibios.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/ppbreg.h>
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#include <i386/pci/pci_bus_fixup.h>
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#include <i386/pci/pcibios.h>
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/* this array lists the parent for each bus number */
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int pci_bus_parent[256];
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/* this array lists the pcitag to program each bridge */
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pcitag_t pci_bus_tag[256];
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static void pci_bridge_reset(pci_chipset_tag_t, pcitag_t, void *);
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int
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pci_bus_fixup(pci_chipset_tag_t pc, int bus)
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{
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static int bus_total;
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static int bridge_cnt;
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int device, maxdevs, function, nfuncs, bridge, bus_max, bus_sub;
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const struct pci_quirkdata *qd;
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pcireg_t reg;
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pcitag_t tag;
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bus_max = bus;
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bus_sub = 0;
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if (++bus_total > 256)
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panic("pci_bus_fixup: more than 256 PCI busses?");
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/* Reset bridge configuration on this bus */
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pci_bridge_foreach(pc, bus, bus, pci_bridge_reset, 0);
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maxdevs = pci_bus_maxdevs(pc, bus);
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for (device = 0; device < maxdevs; device++) {
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tag = pci_make_tag(pc, bus, device, 0);
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reg = pci_conf_read(pc, tag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(reg) == 0)
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continue;
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qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
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reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
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if (PCI_HDRTYPE_MULTIFN(reg) ||
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(qd != NULL &&
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(qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0))
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nfuncs = 8;
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else
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nfuncs = 1;
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for (function = 0; function < nfuncs; function++) {
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tag = pci_make_tag(pc, bus, device, function);
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reg = pci_conf_read(pc, tag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(reg) == 0)
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continue;
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#ifdef PCIBIOSVERBOSE
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printf("PCI fixup examining %02x:%02x\n",
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PCI_VENDOR(reg), PCI_PRODUCT(reg));
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#endif
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reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
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if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
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(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
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PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
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/* Assign the bridge #. */
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bridge = bridge_cnt++;
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/* Assign the bridge's secondary bus #. */
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bus_max++;
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reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
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reg &= 0xff000000;
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reg |= bus | (bus_max << 8) | (0xff << 16);
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pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
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/* Scan subordinate bus. */
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bus_sub = pci_bus_fixup(pc, bus_max);
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/* Configure the bridge. */
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reg &= 0xff000000;
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reg |= bus | (bus_max << 8) | (bus_sub << 16);
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pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
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/* record relationship */
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pci_bus_parent[bus_max]=bus;
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pci_bus_tag[bus_max]=tag;
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#ifdef PCIBIOSVERBOSE
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printf("PCI bridge %d: primary %d, "
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"secondary %d, subordinate %d\n",
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bridge, bus, bus_max, bus_sub);
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#endif
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/* Next bridge's secondary bus #. */
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bus_max = (bus_sub > bus_max) ?
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bus_sub : bus_max;
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}
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}
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}
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return (bus_max); /* last # of subordinate bus */
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}
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/* Reset bus-bridge configuration */
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void
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pci_bridge_reset(pci_chipset_tag_t pc, pcitag_t tag, void *ctx)
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{
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pcireg_t reg;
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reg = pci_conf_read(pc, tag, PPB_REG_BUSINFO);
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reg &= 0xff000000;
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reg |= 0x00ffffff; /* max bus # */
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pci_conf_write(pc, tag, PPB_REG_BUSINFO, reg);
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}
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