155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
/* $NetBSD: cache_sh4.h,v 1.11 2006/03/04 01:55:03 uwe Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH4: SH7750 SH7750S SH7750R SH7751 SH7751R
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*/
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#ifndef _SH3_CACHE_SH4_H_
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#define _SH3_CACHE_SH4_H_
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#include <sh3/devreg.h>
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#ifdef _KERNEL
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#define SH4_ICACHE_SIZE 8192
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#define SH4_DCACHE_SIZE 16384
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#define SH4_EMODE_ICACHE_SIZE 16384
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#define SH4_EMODE_DCACHE_SIZE 32768
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#define SH4_CACHE_LINESZ 32
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#define SH4_CCR 0xff00001c
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#define SH4_CCR_EMODE 0x80000000
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#define SH4_CCR_IIX 0x00008000
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#define SH4_CCR_ICI 0x00000800
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#define SH4_CCR_ICE 0x00000100
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#define SH4_CCR_OIX 0x00000080
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#define SH4_CCR_ORA 0x00000020
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#define SH4_CCR_OCI 0x00000008
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#define SH4_CCR_CB 0x00000004
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#define SH4_CCR_WT 0x00000002
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#define SH4_CCR_OCE 0x00000001
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#define SH4_QACR0 0xff000038
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#define SH4_QACR1 0xff00003c
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#define SH4_QACR_AREA_SHIFT 2
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#define SH4_QACR_AREA_MASK 0x0000001c
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/* I-cache address/data array */
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#define SH4_CCIA 0xf0000000
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/* address specification */
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#define CCIA_A 0x00000008 /* associate bit */
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#define CCIA_ENTRY_SHIFT 5 /* line size 32B */
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#define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */
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#define CCIA_EMODE_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */
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/* data specification */
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#define CCIA_V 0x00000001
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#define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
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#define SH4_CCID 0xf1000000
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/* address specification */
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#define CCID_L_SHIFT 2
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#define CCID_L_MASK 0x1c /* line-size is 32B */
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#define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */
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/* D-cache address/data array */
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#define SH4_CCDA 0xf4000000
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/* address specification */
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#define CCDA_A 0x00000008 /* associate bit */
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#define CCDA_ENTRY_SHIFT 5 /* line size 32B */
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#define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */
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/* data specification */
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#define CCDA_V 0x00000001
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#define CCDA_U 0x00000002
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#define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */
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#define SH4_CCDD 0xf5000000
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/* Store Queue */
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#define SH4_SQ 0xe0000000
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/*
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* cache flush macro for locore level code.
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*/
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#define SH4_CACHE_FLUSH() \
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do { \
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uint32_t __e, __a; \
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\
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/* D-cache */ \
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for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
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} \
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/* I-cache */ \
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for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\
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__a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= ~(CCIA_V); \
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} \
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} while(/*CONSTCOND*/0)
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#define SH4_EMODE_CACHE_FLUSH() \
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do { \
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uint32_t __e, __a; \
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\
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/* D-cache */ \
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for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
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__a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \
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} \
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/* I-cache */ \
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for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\
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__a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \
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(*(volatile uint32_t *)__a) &= ~(CCIA_V); \
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} \
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} while(/*CONSTCOND*/0)
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#define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#if defined(SH4_CACHE_DISABLE_EMODE)
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#define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH()
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#else
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#define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
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#define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH()
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#endif
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#ifndef _LOCORE
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extern void sh4_cache_config(void);
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#endif
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#endif /* _KERNEL */
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#endif /* !_SH3_CACHE_SH4_H_ */
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