489 lines
13 KiB
C
489 lines
13 KiB
C
/* $NetBSD: cia.c,v 1.56 2000/06/29 08:58:45 mrg Exp $ */
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/*-
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* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "opt_dec_eb164.h"
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#include "opt_dec_kn20aa.h"
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#include "opt_dec_550.h"
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#include "opt_dec_1000a.h"
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#include "opt_dec_1000.h"
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: cia.c,v 1.56 2000/06/29 08:58:45 mrg Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/autoconf.h>
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#include <machine/rpb.h>
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#include <machine/sysarch.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#ifdef DEC_KN20AA
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#include <alpha/pci/pci_kn20aa.h>
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#endif
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#ifdef DEC_EB164
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#include <alpha/pci/pci_eb164.h>
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#endif
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#ifdef DEC_550
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#include <alpha/pci/pci_550.h>
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#endif
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#ifdef DEC_1000A
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#include <alpha/pci/pci_1000a.h>
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#endif
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#ifdef DEC_1000
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#include <alpha/pci/pci_1000.h>
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#endif
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int ciamatch __P((struct device *, struct cfdata *, void *));
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void ciaattach __P((struct device *, struct device *, void *));
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struct cfattach cia_ca = {
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sizeof(struct cia_softc), ciamatch, ciaattach,
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};
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extern struct cfdriver cia_cd;
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static int ciaprint __P((void *, const char *pnp));
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int cia_bus_get_window __P((int, int,
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struct alpha_bus_space_translation *));
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/* There can be only one. */
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int ciafound;
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struct cia_config cia_configuration;
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/*
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* This determines if we attempt to use BWX for PCI bus and config space
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* access. Some systems, notably with Pyxis, don't fare so well unless
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* BWX is used.
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*
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* EXCEPT! Some devices have a really hard time if BWX is used (WHY?!).
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* So, we decouple the uses for PCI config space and PCI bus space.
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*
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* FURTHERMORE! The Pyxis, most notably earlier revs, really don't
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* do so well if you don't use BWX for bus access. So we default to
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* forcing BWX on those chips.
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*
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* Geez.
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*/
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#ifndef CIA_PCI_USE_BWX
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#define CIA_PCI_USE_BWX 1
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#endif
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#ifndef CIA_BUS_USE_BWX
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#define CIA_BUS_USE_BWX 0
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#endif
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#ifndef CIA_PYXIS_FORCE_BWX
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#define CIA_PYXIS_FORCE_BWX 0
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#endif
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int cia_pci_use_bwx = CIA_PCI_USE_BWX;
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int cia_bus_use_bwx = CIA_BUS_USE_BWX;
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int cia_pyxis_force_bwx = CIA_PYXIS_FORCE_BWX;
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int
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ciamatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct mainbus_attach_args *ma = aux;
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/* Make sure that we're looking for a CIA. */
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if (strcmp(ma->ma_name, cia_cd.cd_name) != 0)
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return (0);
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if (ciafound)
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return (0);
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return (1);
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}
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/*
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* Set up the chipset's function pointers.
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*/
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void
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cia_init(ccp, mallocsafe)
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struct cia_config *ccp;
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int mallocsafe;
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{
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int pci_use_bwx = cia_pci_use_bwx;
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int bus_use_bwx = cia_bus_use_bwx;
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ccp->cc_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
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ccp->cc_hae_io = REGVAL(CIA_CSR_HAE_IO);
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ccp->cc_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
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/*
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* Determine if we have a Pyxis. Only two systypes can
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* have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
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* and the DEC_550 systype (Miata).
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*/
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if ((cputype == ST_EB164 &&
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(hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
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cputype == ST_DEC_550) {
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ccp->cc_flags |= CCF_ISPYXIS;
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if (cia_pyxis_force_bwx)
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pci_use_bwx = bus_use_bwx = 1;
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}
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/*
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* ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
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*/
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if (ccp->cc_rev >= 2 || (ccp->cc_flags & CCF_ISPYXIS) != 0)
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ccp->cc_cnfg = REGVAL(CIA_CSR_CNFG);
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else
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ccp->cc_cnfg = 0;
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/*
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* Use BWX iff:
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*
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* - It hasn't been disbled by the user,
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* - it's enabled in CNFG,
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* - we're implementation version ev5,
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* - BWX is enabled in the CPU's capabilities mask (yes,
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* the bit is really cleared if the capability exists...)
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*/
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if ((pci_use_bwx || bus_use_bwx) &&
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(ccp->cc_cnfg & CNFG_BWEN) != 0 &&
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(cpu_amask & ALPHA_AMASK_BWX) != 0) {
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u_int32_t ctrl;
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if (pci_use_bwx)
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ccp->cc_flags |= CCF_PCI_USE_BWX;
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if (bus_use_bwx)
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ccp->cc_flags |= CCF_BUS_USE_BWX;
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/*
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* For whatever reason, the firmware seems to enable PCI
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* loopback mode if it also enables BWX. Make sure it's
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* enabled if we have an old, buggy firmware rev.
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*/
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alpha_mb();
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ctrl = REGVAL(CIA_CSR_CTRL);
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if ((ctrl & CTRL_PCI_LOOP_EN) == 0) {
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REGVAL(CIA_CSR_CTRL) = ctrl | CTRL_PCI_LOOP_EN;
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alpha_mb();
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}
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}
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if (!ccp->cc_initted) {
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/* don't do these twice since they set up extents */
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if (ccp->cc_flags & CCF_BUS_USE_BWX) {
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cia_bwx_bus_io_init(&ccp->cc_iot, ccp);
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cia_bwx_bus_mem_init(&ccp->cc_memt, ccp);
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/*
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* We have one window for both PCI I/O and MEM
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* in BWX mode.
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*/
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alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 1;
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alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 1;
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} else {
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cia_swiz_bus_io_init(&ccp->cc_iot, ccp);
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cia_swiz_bus_mem_init(&ccp->cc_memt, ccp);
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/*
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* We have two I/O windows and 4 MEM windows in
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* SWIZ mode.
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*/
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alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_IO] = 2;
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alpha_bus_window_count[ALPHA_BUS_TYPE_PCI_MEM] = 4;
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}
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alpha_bus_get_window = cia_bus_get_window;
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}
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ccp->cc_mallocsafe = mallocsafe;
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cia_pci_init(&ccp->cc_pc, ccp);
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alpha_pci_chipset = &ccp->cc_pc;
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ccp->cc_initted = 1;
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}
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void
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ciaattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct cia_softc *sc = (struct cia_softc *)self;
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struct cia_config *ccp;
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struct pcibus_attach_args pba;
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char bits[64];
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const char *name;
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int pass;
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/* note that we've attached the chipset; can't have 2 CIAs. */
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ciafound = 1;
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/*
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* set up the chipset's info; done once at console init time
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* (maybe), but we must do it here as well to take care of things
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* that need to use memory allocation.
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*/
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ccp = sc->sc_ccp = &cia_configuration;
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cia_init(ccp, 1);
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if (ccp->cc_flags & CCF_ISPYXIS) {
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name = "Pyxis";
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pass = ccp->cc_rev;
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} else {
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name = "ALCOR/ALCOR2";
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pass = ccp->cc_rev + 1;
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}
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printf(": DECchip 2117x Core Logic Chipset (%s), pass %d\n",
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name, pass);
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if (ccp->cc_cnfg)
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printf("%s: extended capabilities: %s\n", self->dv_xname,
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bitmask_snprintf(ccp->cc_cnfg, CIA_CSR_CNFG_BITS,
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bits, sizeof(bits)));
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switch (ccp->cc_flags & (CCF_PCI_USE_BWX|CCF_BUS_USE_BWX)) {
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case CCF_PCI_USE_BWX|CCF_BUS_USE_BWX:
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name = "PCI config and bus";
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break;
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case CCF_PCI_USE_BWX:
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name = "PCI config";
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break;
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case CCF_BUS_USE_BWX:
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name = "bus";
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break;
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default:
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name = NULL;
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break;
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}
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if (name != NULL)
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printf("%s: using BWX for %s access\n", self->dv_xname, name);
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#ifdef DEC_550
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if (cputype == ST_DEC_550 &&
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(hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
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/*
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* Miata 1 systems have a bug: DMA cannot cross
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* an 8k boundary! Make sure PCI read prefetching
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* is disabled on these chips. Note that secondary
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* PCI busses don't have this problem, because of
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* the way PPBs handle PCI read requests.
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*
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* In the 21174 Technical Reference Manual, this is
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* actually documented as "Pyxis Pass 1", but apparently
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* there are chips that report themselves as "Pass 1"
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* which do not have the bug! Miatas with the Cypress
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* PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
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* have the bug, so we use this check.
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*
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* NOTE: This bug is actually worked around in cia_dma.c,
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* when direct-mapped DMA maps are created.
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*
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* XXX WE NEED TO THINK ABOUT HOW TO HANDLE THIS FOR
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* XXX SGMAP DMA MAPPINGS!
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*/
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u_int32_t ctrl;
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/* XXX no bets... */
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printf("%s: WARNING: Pyxis pass 1 DMA bug; no bets...\n",
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self->dv_xname);
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ccp->cc_flags |= CCF_PYXISBUG;
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alpha_mb();
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ctrl = REGVAL(CIA_CSR_CTRL);
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ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
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REGVAL(CIA_CSR_CTRL) = ctrl;
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alpha_mb();
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}
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#endif /* DEC_550 */
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cia_dma_init(ccp);
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switch (cputype) {
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#ifdef DEC_KN20AA
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case ST_DEC_KN20AA:
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pci_kn20aa_pickintr(ccp);
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break;
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#endif
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#ifdef DEC_EB164
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case ST_EB164:
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pci_eb164_pickintr(ccp);
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break;
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#endif
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#ifdef DEC_550
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case ST_DEC_550:
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pci_550_pickintr(ccp);
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break;
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#endif
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#ifdef DEC_1000A
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case ST_DEC_1000A:
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pci_1000a_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
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&ccp->cc_pc);
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break;
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#endif
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#ifdef DEC_1000
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case ST_DEC_1000:
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pci_1000_pickintr(ccp, &ccp->cc_iot, &ccp->cc_memt,
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&ccp->cc_pc);
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break;
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#endif
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default:
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panic("ciaattach: shouldn't be here, really...");
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}
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pba.pba_busname = "pci";
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pba.pba_iot = &ccp->cc_iot;
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pba.pba_memt = &ccp->cc_memt;
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pba.pba_dmat =
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alphabus_dma_get_tag(&ccp->cc_dmat_direct, ALPHA_BUS_PCI);
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pba.pba_pc = &ccp->cc_pc;
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pba.pba_bus = 0;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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if ((ccp->cc_flags & CCF_PYXISBUG) == 0)
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pba.pba_flags |= PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY |
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PCI_FLAGS_MWI_OKAY;
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config_found(self, &pba, ciaprint);
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}
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static int
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ciaprint(aux, pnp)
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void *aux;
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const char *pnp;
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{
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register struct pcibus_attach_args *pba = aux;
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/* only PCIs can attach to CIAs; easy. */
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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int
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cia_bus_get_window(type, window, abst)
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int type, window;
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struct alpha_bus_space_translation *abst;
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{
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struct cia_config *ccp = &cia_configuration;
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bus_space_tag_t st;
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switch (type) {
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case ALPHA_BUS_TYPE_PCI_IO:
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st = &ccp->cc_iot;
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break;
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case ALPHA_BUS_TYPE_PCI_MEM:
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st = &ccp->cc_memt;
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break;
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default:
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panic("cia_bus_get_window");
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}
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return (alpha_bus_space_get_window(st, window, abst));
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}
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void
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cia_pyxis_intr_enable(irq, onoff)
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int irq, onoff;
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{
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u_int64_t imask;
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int s;
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#if 0
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printf("cia_pyxis_intr_enable: %s %d\n",
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onoff ? "enabling" : "disabling", irq);
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#endif
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s = splhigh();
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alpha_mb();
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imask = REGVAL64(PYXIS_INT_MASK);
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if (onoff)
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imask |= (1UL << irq);
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else
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imask &= ~(1UL << irq);
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REGVAL64(PYXIS_INT_MASK) = imask;
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alpha_mb();
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splx(s);
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}
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