579 lines
16 KiB
C
579 lines
16 KiB
C
/* $NetBSD: isp_pci.c,v 1.35 1999/02/09 00:35:35 mjacob Exp $ */
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/* release_02_05_99 */
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/*
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* PCI specific probe and attach routines for Qlogic ISP SCSI adapters.
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*
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*---------------------------------------
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* Copyright (c) 1997, 1998 by Matthew Jacob
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* NASA/Ames Research Center
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* All rights reserved.
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*---------------------------------------
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <dev/ic/isp_netbsd.h>
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#include <dev/microcode/isp/asm_pci.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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static u_int16_t isp_pci_rd_reg __P((struct ispsoftc *, int));
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static void isp_pci_wr_reg __P((struct ispsoftc *, int, u_int16_t));
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static int isp_pci_mbxdma __P((struct ispsoftc *));
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static int isp_pci_dmasetup __P((struct ispsoftc *, struct scsipi_xfer *,
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ispreq_t *, u_int8_t *, u_int8_t));
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static void isp_pci_dmateardown __P((struct ispsoftc *, struct scsipi_xfer *,
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u_int32_t));
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static void isp_pci_reset1 __P((struct ispsoftc *));
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static void isp_pci_dumpregs __P((struct ispsoftc *));
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static int isp_pci_intr __P((void *));
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static struct ispmdvec mdvec = {
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isp_pci_rd_reg,
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isp_pci_wr_reg,
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isp_pci_mbxdma,
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isp_pci_dmasetup,
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isp_pci_dmateardown,
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NULL,
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isp_pci_reset1,
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isp_pci_dumpregs,
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ISP_RISC_CODE,
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ISP_CODE_LENGTH,
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ISP_CODE_ORG,
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ISP_CODE_VERSION,
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BIU_BURST_ENABLE|BIU_PCI_CONF1_FIFO_64,
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0
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};
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static struct ispmdvec mdvec_2100 = {
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isp_pci_rd_reg,
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isp_pci_wr_reg,
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isp_pci_mbxdma,
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isp_pci_dmasetup,
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isp_pci_dmateardown,
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NULL,
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isp_pci_reset1,
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isp_pci_dumpregs,
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ISP2100_RISC_CODE,
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ISP2100_CODE_LENGTH,
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ISP2100_CODE_ORG,
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ISP2100_CODE_VERSION,
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0, /* Irrelevant to the 2100 */
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0
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};
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#define PCI_QLOGIC_ISP \
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((PCI_PRODUCT_QLOGIC_ISP1020 << 16) | PCI_VENDOR_QLOGIC)
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#ifndef PCI_PRODUCT_QLOGIC_ISP2100
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#define PCI_PRODUCT_QLOGIC_ISP2100 0x2100
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#endif
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#define PCI_QLOGIC_ISP2100 \
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((PCI_PRODUCT_QLOGIC_ISP2100 << 16) | PCI_VENDOR_QLOGIC)
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#define IO_MAP_REG 0x10
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#define MEM_MAP_REG 0x14
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static int isp_pci_probe __P((struct device *, struct cfdata *, void *));
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static void isp_pci_attach __P((struct device *, struct device *, void *));
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struct isp_pcisoftc {
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struct ispsoftc pci_isp;
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pci_chipset_tag_t pci_pc;
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pcitag_t pci_tag;
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bus_space_tag_t pci_st;
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bus_space_handle_t pci_sh;
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bus_dma_tag_t pci_dmat;
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bus_dmamap_t pci_scratch_dmap; /* for fcp only */
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bus_dmamap_t pci_rquest_dmap;
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bus_dmamap_t pci_result_dmap;
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bus_dmamap_t pci_xfer_dmap[MAXISPREQUEST];
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void * pci_ih;
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};
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struct cfattach isp_pci_ca = {
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sizeof (struct isp_pcisoftc), isp_pci_probe, isp_pci_attach
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};
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static int
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isp_pci_probe(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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if (pa->pa_id == PCI_QLOGIC_ISP ||
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pa->pa_id == PCI_QLOGIC_ISP2100) {
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return (1);
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} else {
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return (0);
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}
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}
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static void
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isp_pci_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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#ifdef DEBUG
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static char oneshot = 1;
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#endif
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u_int32_t data;
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struct pci_attach_args *pa = aux;
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struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) self;
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struct ispsoftc *isp = &pcs->pci_isp;
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bus_space_tag_t st, iot, memt;
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bus_space_handle_t sh, ioh, memh;
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pci_intr_handle_t ih;
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const char *intrstr;
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int ioh_valid, memh_valid, i;
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ISP_LOCKVAL_DECL;
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ioh_valid = (pci_mapreg_map(pa, IO_MAP_REG,
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PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, NULL, NULL) == 0);
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memh_valid = (pci_mapreg_map(pa, MEM_MAP_REG,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&memt, &memh, NULL, NULL) == 0);
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if (memh_valid) {
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st = memt;
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sh = memh;
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} else if (ioh_valid) {
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st = iot;
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sh = ioh;
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} else {
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printf(": unable to map device registers\n");
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return;
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}
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printf("\n");
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pcs->pci_st = st;
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pcs->pci_sh = sh;
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pcs->pci_dmat = pa->pa_dmat;
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pcs->pci_pc = pa->pa_pc;
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pcs->pci_tag = pa->pa_tag;
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if (pa->pa_id == PCI_QLOGIC_ISP) {
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isp->isp_mdvec = &mdvec;
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isp->isp_type = ISP_HA_SCSI_UNKNOWN;
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isp->isp_param = malloc(sizeof (sdparam), M_DEVBUF, M_NOWAIT);
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if (isp->isp_param == NULL) {
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printf("%s: couldn't allocate sdparam table\n",
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isp->isp_name);
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return;
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}
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bzero(isp->isp_param, sizeof (sdparam));
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} else if (pa->pa_id == PCI_QLOGIC_ISP2100) {
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isp->isp_mdvec = &mdvec_2100;
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isp->isp_type = ISP_HA_FC_2100;
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isp->isp_param = malloc(sizeof (fcparam), M_DEVBUF, M_NOWAIT);
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if (isp->isp_param == NULL) {
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printf("%s: couldn't allocate fcparam table\n",
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isp->isp_name);
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return;
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}
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bzero(isp->isp_param, sizeof (fcparam));
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} else {
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return;
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}
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/*
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* Make sure that command register set sanely.
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*/
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data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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data |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_INVALIDATE_ENABLE;
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/*
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* Not so sure about these- but I think it's important that they get
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* enabled......
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*/
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data |= PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, data);
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/*
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* Make sure that latency timer and cache line size is set sanely.
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*/
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data = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
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data &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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data &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
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data |= (0x40 << PCI_LATTIMER_SHIFT);
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data |= (0x10 << PCI_CACHELINE_SHIFT);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, data);
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#ifdef DEBUG
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if (oneshot) {
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oneshot = 0;
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printf("Qlogic ISP Driver, NetBSD (pci) Platform Version "
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"%d.%d Core Version %d.%d\n",
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ISP_PLATFORM_VERSION_MAJOR, ISP_PLATFORM_VERSION_MINOR,
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ISP_CORE_VERSION_MAJOR, ISP_CORE_VERSION_MINOR);
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}
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#endif
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ISP_LOCK(isp);
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isp_reset(isp);
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if (isp->isp_state != ISP_RESETSTATE) {
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ISP_UNLOCK(isp);
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free(isp->isp_param, M_DEVBUF);
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return;
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}
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isp_init(isp);
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if (isp->isp_state != ISP_INITSTATE) {
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isp_uninit(isp);
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ISP_UNLOCK(isp);
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free(isp->isp_param, M_DEVBUF);
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return;
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}
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if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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printf("%s: couldn't map interrupt\n", isp->isp_name);
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isp_uninit(isp);
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ISP_UNLOCK(isp);
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free(isp->isp_param, M_DEVBUF);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih);
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if (intrstr == NULL)
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intrstr = "<I dunno>";
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pcs->pci_ih =
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pci_intr_establish(pa->pa_pc, ih, IPL_BIO, isp_pci_intr, isp);
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if (pcs->pci_ih == NULL) {
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printf("%s: couldn't establish interrupt at %s\n",
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isp->isp_name, intrstr);
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isp_uninit(isp);
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ISP_UNLOCK(isp);
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free(isp->isp_param, M_DEVBUF);
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return;
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}
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printf("%s: interrupting at %s\n", isp->isp_name, intrstr);
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/*
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* Create the DMA maps for the data transfers.
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*/
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for (i = 0; i < RQUEST_QUEUE_LEN; i++) {
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if (bus_dmamap_create(pcs->pci_dmat, MAXPHYS,
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(MAXPHYS / NBPG) + 1, MAXPHYS, 0, BUS_DMA_NOWAIT,
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&pcs->pci_xfer_dmap[i])) {
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printf("%s: can't create dma maps\n",
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isp->isp_name);
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isp_uninit(isp);
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ISP_UNLOCK(isp);
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return;
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}
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}
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/*
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* Do Generic attach now.
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*/
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isp_attach(isp);
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if (isp->isp_state != ISP_RUNSTATE) {
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isp_uninit(isp);
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free(isp->isp_param, M_DEVBUF);
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}
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ISP_UNLOCK(isp);
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}
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#define PCI_BIU_REGS_OFF BIU_REGS_OFF
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static u_int16_t
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isp_pci_rd_reg(isp, regoff)
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struct ispsoftc *isp;
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int regoff;
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{
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u_int16_t rv;
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struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
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int offset, oldsxp = 0;
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if ((regoff & BIU_BLOCK) != 0) {
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offset = PCI_BIU_REGS_OFF;
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} else if ((regoff & MBOX_BLOCK) != 0) {
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if (isp->isp_type & ISP_HA_SCSI)
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offset = PCI_MBOX_REGS_OFF;
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else
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offset = PCI_MBOX_REGS2100_OFF;
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} else if ((regoff & SXP_BLOCK) != 0) {
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offset = PCI_SXP_REGS_OFF;
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/*
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* We will assume that someone has paused the RISC processor.
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*/
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oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
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isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
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} else {
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offset = PCI_RISC_REGS_OFF;
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}
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regoff &= 0xff;
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offset += regoff;
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rv = bus_space_read_2(pcs->pci_st, pcs->pci_sh, offset);
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if ((regoff & SXP_BLOCK) != 0) {
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isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
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}
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return (rv);
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}
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static void
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isp_pci_wr_reg(isp, regoff, val)
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struct ispsoftc *isp;
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int regoff;
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u_int16_t val;
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{
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struct isp_pcisoftc *pcs = (struct isp_pcisoftc *) isp;
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int offset, oldsxp = 0;
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if ((regoff & BIU_BLOCK) != 0) {
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offset = PCI_BIU_REGS_OFF;
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} else if ((regoff & MBOX_BLOCK) != 0) {
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if (isp->isp_type & ISP_HA_SCSI)
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offset = PCI_MBOX_REGS_OFF;
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else
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offset = PCI_MBOX_REGS2100_OFF;
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} else if ((regoff & SXP_BLOCK) != 0) {
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offset = PCI_SXP_REGS_OFF;
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/*
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* We will assume that someone has paused the RISC processor.
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*/
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oldsxp = isp_pci_rd_reg(isp, BIU_CONF1);
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isp_pci_wr_reg(isp, BIU_CONF1, oldsxp & ~BIU_PCI_CONF1_SXP);
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} else {
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offset = PCI_RISC_REGS_OFF;
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}
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regoff &= 0xff;
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offset += regoff;
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bus_space_write_2(pcs->pci_st, pcs->pci_sh, offset, val);
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if ((regoff & SXP_BLOCK) != 0) {
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isp_pci_wr_reg(isp, BIU_CONF1, oldsxp);
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}
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}
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static int
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isp_pci_mbxdma(isp)
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struct ispsoftc *isp;
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{
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struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
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bus_dma_segment_t seg;
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bus_size_t len;
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fcparam *fcp;
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int rseg;
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/*
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* Allocate and map the request queue.
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*/
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len = ISP_QUEUE_SIZE(RQUEST_QUEUE_LEN);
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if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
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BUS_DMA_NOWAIT) ||
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bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
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(caddr_t *)&isp->isp_rquest, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
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return (1);
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if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
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&pci->pci_rquest_dmap) ||
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bus_dmamap_load(pci->pci_dmat, pci->pci_rquest_dmap,
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(caddr_t)isp->isp_rquest, len, NULL, BUS_DMA_NOWAIT))
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return (1);
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isp->isp_rquest_dma = pci->pci_rquest_dmap->dm_segs[0].ds_addr;
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/*
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* Allocate and map the result queue.
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*/
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len = ISP_QUEUE_SIZE(RESULT_QUEUE_LEN);
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if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
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BUS_DMA_NOWAIT) ||
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bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
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(caddr_t *)&isp->isp_result, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
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return (1);
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if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
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&pci->pci_result_dmap) ||
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bus_dmamap_load(pci->pci_dmat, pci->pci_result_dmap,
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(caddr_t)isp->isp_result, len, NULL, BUS_DMA_NOWAIT))
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return (1);
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isp->isp_result_dma = pci->pci_result_dmap->dm_segs[0].ds_addr;
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if (isp->isp_type & ISP_HA_SCSI) {
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return (0);
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}
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|
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fcp = isp->isp_param;
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len = ISP2100_SCRLEN;
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if (bus_dmamem_alloc(pci->pci_dmat, len, NBPG, 0, &seg, 1, &rseg,
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BUS_DMA_NOWAIT) ||
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bus_dmamem_map(pci->pci_dmat, &seg, rseg, len,
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(caddr_t *)&fcp->isp_scratch, BUS_DMA_NOWAIT|BUS_DMA_COHERENT))
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return (1);
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if (bus_dmamap_create(pci->pci_dmat, len, 1, len, 0, BUS_DMA_NOWAIT,
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&pci->pci_scratch_dmap) ||
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bus_dmamap_load(pci->pci_dmat, pci->pci_scratch_dmap,
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(caddr_t)fcp->isp_scratch, len, NULL, BUS_DMA_NOWAIT))
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return (1);
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fcp->isp_scdma = pci->pci_scratch_dmap->dm_segs[0].ds_addr;
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return (0);
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}
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|
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static int
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isp_pci_dmasetup(isp, xs, rq, iptrp, optr)
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struct ispsoftc *isp;
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struct scsipi_xfer *xs;
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ispreq_t *rq;
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u_int8_t *iptrp;
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u_int8_t optr;
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{
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struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
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bus_dmamap_t dmap = pci->pci_xfer_dmap[rq->req_handle - 1];
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ispcontreq_t *crq;
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int segcnt, seg, error, ovseg, seglim, drq;
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|
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if (xs->datalen == 0) {
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rq->req_seg_count = 1;
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goto mbxsync;
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}
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|
|
if (rq->req_handle > RQUEST_QUEUE_LEN || rq->req_handle < 1) {
|
|
panic("%s: bad handle (%d) in isp_pci_dmasetup\n",
|
|
isp->isp_name, rq->req_handle);
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
if (xs->flags & SCSI_DATA_IN) {
|
|
drq = REQFLAG_DATA_IN;
|
|
} else {
|
|
drq = REQFLAG_DATA_OUT;
|
|
}
|
|
|
|
if (isp->isp_type & ISP_HA_FC) {
|
|
seglim = ISP_RQDSEG_T2;
|
|
((ispreqt2_t *)rq)->req_totalcnt = xs->datalen;
|
|
((ispreqt2_t *)rq)->req_flags |= drq;
|
|
} else {
|
|
seglim = ISP_RQDSEG;
|
|
rq->req_flags |= drq;
|
|
}
|
|
error = bus_dmamap_load(pci->pci_dmat, dmap, xs->data, xs->datalen,
|
|
NULL, xs->flags & SCSI_NOSLEEP ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
|
|
if (error) {
|
|
XS_SETERR(xs, HBA_BOTCH);
|
|
return (CMD_COMPLETE);
|
|
}
|
|
|
|
segcnt = dmap->dm_nsegs;
|
|
|
|
for (seg = 0, rq->req_seg_count = 0;
|
|
seg < segcnt && rq->req_seg_count < seglim;
|
|
seg++, rq->req_seg_count++) {
|
|
if (isp->isp_type & ISP_HA_FC) {
|
|
ispreqt2_t *rq2 = (ispreqt2_t *)rq;
|
|
rq2->req_dataseg[rq2->req_seg_count].ds_count =
|
|
dmap->dm_segs[seg].ds_len;
|
|
rq2->req_dataseg[rq2->req_seg_count].ds_base =
|
|
dmap->dm_segs[seg].ds_addr;
|
|
} else {
|
|
rq->req_dataseg[rq->req_seg_count].ds_count =
|
|
dmap->dm_segs[seg].ds_len;
|
|
rq->req_dataseg[rq->req_seg_count].ds_base =
|
|
dmap->dm_segs[seg].ds_addr;
|
|
}
|
|
}
|
|
|
|
if (seg == segcnt)
|
|
goto dmasync;
|
|
|
|
do {
|
|
crq = (ispcontreq_t *)
|
|
ISP_QUEUE_ENTRY(isp->isp_rquest, *iptrp);
|
|
*iptrp = (*iptrp + 1) & (RQUEST_QUEUE_LEN - 1);
|
|
if (*iptrp == optr) {
|
|
printf("%s: Request Queue Overflow++\n",
|
|
isp->isp_name);
|
|
bus_dmamap_unload(pci->pci_dmat, dmap);
|
|
XS_SETERR(xs, HBA_BOTCH);
|
|
return (CMD_COMPLETE);
|
|
}
|
|
rq->req_header.rqs_entry_count++;
|
|
bzero((void *)crq, sizeof (*crq));
|
|
crq->req_header.rqs_entry_count = 1;
|
|
crq->req_header.rqs_entry_type = RQSTYPE_DATASEG;
|
|
|
|
for (ovseg = 0; seg < segcnt && ovseg < ISP_CDSEG;
|
|
rq->req_seg_count++, seg++, ovseg++) {
|
|
crq->req_dataseg[ovseg].ds_count =
|
|
dmap->dm_segs[seg].ds_len;
|
|
crq->req_dataseg[ovseg].ds_base =
|
|
dmap->dm_segs[seg].ds_addr;
|
|
}
|
|
} while (seg < segcnt);
|
|
|
|
dmasync:
|
|
bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
|
|
(xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD :
|
|
BUS_DMASYNC_PREWRITE);
|
|
|
|
mbxsync:
|
|
|
|
bus_dmamap_sync(pci->pci_dmat, pci->pci_rquest_dmap, 0,
|
|
pci->pci_rquest_dmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
|
|
return (CMD_QUEUED);
|
|
}
|
|
|
|
static int
|
|
isp_pci_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct isp_pcisoftc *pci = (struct isp_pcisoftc *)arg;
|
|
bus_dmamap_sync(pci->pci_dmat, pci->pci_result_dmap, 0,
|
|
pci->pci_result_dmap->dm_mapsize, BUS_DMASYNC_POSTREAD);
|
|
return (isp_intr(arg));
|
|
}
|
|
|
|
static void
|
|
isp_pci_dmateardown(isp, xs, handle)
|
|
struct ispsoftc *isp;
|
|
struct scsipi_xfer *xs;
|
|
u_int32_t handle;
|
|
{
|
|
struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
|
|
bus_dmamap_t dmap = pci->pci_xfer_dmap[handle];
|
|
|
|
bus_dmamap_sync(pci->pci_dmat, dmap, 0, dmap->dm_mapsize,
|
|
xs->flags & SCSI_DATA_IN ?
|
|
BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(pci->pci_dmat, dmap);
|
|
}
|
|
|
|
static void
|
|
isp_pci_reset1(isp)
|
|
struct ispsoftc *isp;
|
|
{
|
|
/* Make sure the BIOS is disabled */
|
|
isp_pci_wr_reg(isp, HCCR, PCI_HCCR_CMD_BIOS);
|
|
}
|
|
|
|
static void
|
|
isp_pci_dumpregs(isp)
|
|
struct ispsoftc *isp;
|
|
{
|
|
struct isp_pcisoftc *pci = (struct isp_pcisoftc *)isp;
|
|
printf("%s: PCI Status Command/Status=%x\n", pci->pci_isp.isp_name,
|
|
pci_conf_read(pci->pci_pc, pci->pci_tag, PCI_COMMAND_STATUS_REG));
|
|
}
|