498 lines
12 KiB
C
498 lines
12 KiB
C
/* $NetBSD: ifpga_intr.c,v 1.1 2003/09/06 11:31:21 rearnsha Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef EVBARM_SPL_NOINLINE
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#define EVBARM_SPL_NOINLINE
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#endif
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/*
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* Interrupt support for the Integrator FPGA.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <evbarm/ifpga/ifpgareg.h>
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#include <evbarm/ifpga/ifpgavar.h>
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/* Interrupt handler queues. */
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struct intrq intrq[NIRQ];
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/* Interrupts to mask at each level. */
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int ifpga_imask[NIPL];
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/* Current interrupt priority level. */
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__volatile int current_spl_level;
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/* Interrupts pending. */
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__volatile int ifpga_ipending;
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/* Software copy of the IRQs we have enabled. */
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__volatile uint32_t intr_enabled;
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/* Mask if interrupts steered to FIQs. */
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uint32_t intr_steer;
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/*
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* Map a software interrupt queue index (to the unused bits in the
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* ICU registers -- XXX will need to revisit this if those bits are
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* ever used in future steppings).
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*/
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static const uint32_t si_to_irqbit[SI_NQUEUES] = {
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IFPGA_INTR_bit31, /* SI_SOFT */
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IFPGA_INTR_bit30, /* SI_SOFTCLOCK */
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IFPGA_INTR_bit29, /* SI_SOFTNET */
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IFPGA_INTR_bit28, /* SI_SOFTSERIAL */
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};
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#define SI_TO_IRQBIT(si) (si_to_irqbit[(si)])
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFT, /* SI_SOFT */
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IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
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IPL_SOFTNET, /* SI_SOFTNET */
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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};
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/*
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* Interrupt bit names.
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*/
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const char *ifpga_irqnames[] = {
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"soft", /* 0 */
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"uart 0", /* 1 */
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"uart 1", /* 2 */
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"kbd", /* 3 */
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"mouse", /* 4 */
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"tmr 0", /* 5 */
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"tmr 1 hard", /* 6 */
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"tmr 2 stat", /* 7 */
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"rtc", /* 8 */
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"exp 0", /* 9 */
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"exp 1", /* 10 */
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"exp 2", /* 11 */
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"exp 3", /* 12 */
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"pci 0", /* 13 */
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"pci 1", /* 14 */
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"pci 2", /* 15 */
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"pci 3", /* 16 */
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"V3 br", /* 17 */
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"deg", /* 18 */
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"enum", /* 19 */
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"pci lb", /* 20 */
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"autoPC", /* 21 */
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"irq 22", /* 22 */
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"irq 23", /* 23 */
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"irq 24", /* 24 */
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"irq 25", /* 25 */
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"irq 26", /* 26 */
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"irq 27", /* 27 */
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"irq 28", /* 28 */
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"irq 29", /* 29 */
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"irq 30", /* 30 */
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"irq 31", /* 31 */
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};
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void ifpga_intr_dispatch(struct clockframe *frame);
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extern struct ifpga_softc *ifpga_sc;
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static __inline uint32_t
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ifpga_iintsrc_read(void)
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{
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return bus_space_read_4(ifpga_sc->sc_iot, ifpga_sc->sc_irq_ioh,
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IFPGA_INTR_STATUS);
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}
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static __inline void
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ifpga_enable_irq(int irq)
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{
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intr_enabled |= (1U << irq);
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ifpga_set_intrmask();
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}
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static __inline void
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ifpga_disable_irq(int irq)
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{
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intr_enabled &= ~(1U << irq);
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ifpga_set_intrmask();
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}
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/*
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* NOTE: This routine must be called with interrupts disabled in the CPSR.
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*/
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static void
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ifpga_intr_calculate_masks(void)
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{
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struct intrq *iq;
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struct intrhand *ih;
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int irq, ipl;
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/* First, figure out which IPLs each IRQ has. */
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for (irq = 0; irq < NIRQ; irq++) {
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int levels = 0;
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iq = &intrq[irq];
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ifpga_disable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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levels |= (1U << ih->ih_ipl);
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iq->iq_levels = levels;
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}
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/* Next, figure out which IRQs are used by each IPL. */
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for (ipl = 0; ipl < NIPL; ipl++) {
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int irqs = 0;
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for (irq = 0; irq < NIRQ; irq++) {
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if (intrq[irq].iq_levels & (1U << ipl))
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irqs |= (1U << irq);
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}
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ifpga_imask[ipl] = irqs;
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}
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ifpga_imask[IPL_NONE] = 0;
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/*
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* Initialize the soft interrupt masks to block themselves.
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*/
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ifpga_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
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ifpga_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
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ifpga_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
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ifpga_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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ifpga_imask[IPL_SOFTCLOCK] |= ifpga_imask[IPL_SOFT];
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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ifpga_imask[IPL_SOFTNET] |= ifpga_imask[IPL_SOFTCLOCK];
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/*
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* Enforce a heirarchy that gives "slow" device (or devices with
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* limited input buffer space/"real-time" requirements) a better
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* chance at not dropping data.
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*/
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ifpga_imask[IPL_BIO] |= ifpga_imask[IPL_SOFTNET];
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ifpga_imask[IPL_NET] |= ifpga_imask[IPL_BIO];
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ifpga_imask[IPL_SOFTSERIAL] |= ifpga_imask[IPL_NET];
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ifpga_imask[IPL_TTY] |= ifpga_imask[IPL_SOFTSERIAL];
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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ifpga_imask[IPL_VM] |= ifpga_imask[IPL_TTY];
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/*
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* Audio devices are not allowed to perform memory allocation
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* in their interrupt routines, and they have fairly "real-time"
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* requirements, so give them a high interrupt priority.
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*/
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ifpga_imask[IPL_AUDIO] |= ifpga_imask[IPL_VM];
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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ifpga_imask[IPL_CLOCK] |= ifpga_imask[IPL_AUDIO];
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/*
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* splstatclock() must also block the clock.
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*/
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ifpga_imask[IPL_STATCLOCK] |= ifpga_imask[IPL_CLOCK];
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/*
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* splhigh() must block "everything".
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*/
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ifpga_imask[IPL_HIGH] |= ifpga_imask[IPL_STATCLOCK];
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/*
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* XXX We need serial drivers to run at the absolute highest priority
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* in order to avoid overruns, so serial > high.
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*/
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ifpga_imask[IPL_SERIAL] |= ifpga_imask[IPL_HIGH];
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/*
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* Now compute which IRQs must be blocked when servicing any
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* given IRQ.
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*/
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for (irq = 0; irq < NIRQ; irq++) {
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int irqs = (1U << irq);
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iq = &intrq[irq];
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if (TAILQ_FIRST(&iq->iq_list) != NULL)
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ifpga_enable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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irqs |= ifpga_imask[ih->ih_ipl];
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iq->iq_mask = irqs;
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}
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}
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__inline void
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ifpga_do_pending(void)
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{
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static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
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int new, oldirqstate;
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if (__cpu_simple_lock_try(&processing) == 0)
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return;
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new = current_spl_level;
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oldirqstate = disable_interrupts(I32_bit);
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#define DO_SOFTINT(si) \
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if ((ifpga_ipending & ~new) & SI_TO_IRQBIT(si)) { \
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ifpga_ipending &= ~SI_TO_IRQBIT(si); \
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current_spl_level |= ifpga_imask[si_to_ipl[(si)]]; \
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restore_interrupts(oldirqstate); \
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softintr_dispatch(si); \
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oldirqstate = disable_interrupts(I32_bit); \
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current_spl_level = new; \
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}
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DO_SOFTINT(SI_SOFTSERIAL);
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DO_SOFTINT(SI_SOFTNET);
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DO_SOFTINT(SI_SOFTCLOCK);
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DO_SOFTINT(SI_SOFT);
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__cpu_simple_unlock(&processing);
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restore_interrupts(oldirqstate);
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}
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void
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splx(int new)
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{
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ifpga_splx(new);
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}
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int
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_spllower(int ipl)
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{
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return (ifpga_spllower(ipl));
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}
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int
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_splraise(int ipl)
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{
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return (ifpga_splraise(ipl));
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}
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void
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_setsoftintr(int si)
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{
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int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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ifpga_ipending |= SI_TO_IRQBIT(si);
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restore_interrupts(oldirqstate);
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/* Process unmasked pending soft interrupts. */
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if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level)
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ifpga_do_pending();
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}
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/*
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* ifpga_intr_init:
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*
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* Initialize the rest of the interrupt subsystem, making it
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* ready to handle interrupts from devices.
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*/
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void
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ifpga_intr_init(void)
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{
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struct intrq *iq;
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int i;
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intr_enabled = 0;
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for (i = 0; i < NIRQ; i++) {
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iq = &intrq[i];
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TAILQ_INIT(&iq->iq_list);
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evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
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NULL, "ifpga", ifpga_irqnames[i]);
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}
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}
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void
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ifpga_intr_postinit(void)
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{
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ifpga_intr_calculate_masks();
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/* Enable IRQs (don't yet use FIQs). */
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enable_interrupts(I32_bit);
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}
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void *
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ifpga_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
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{
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struct intrq *iq;
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struct intrhand *ih;
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u_int oldirqstate;
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if (irq < 0 || irq > NIRQ)
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panic("ifpga_intr_establish: IRQ %d out of range", irq);
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = func;
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ih->ih_arg = arg;
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ih->ih_ipl = ipl;
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ih->ih_irq = irq;
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iq = &intrq[irq];
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/* All IOP321 interrupts are level-triggered. */
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iq->iq_ist = IST_LEVEL;
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oldirqstate = disable_interrupts(I32_bit);
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TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
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ifpga_intr_calculate_masks();
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restore_interrupts(oldirqstate);
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return (ih);
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}
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void
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ifpga_intr_disestablish(void *cookie)
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{
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struct intrhand *ih = cookie;
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struct intrq *iq = &intrq[ih->ih_irq];
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int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
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ifpga_intr_calculate_masks();
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restore_interrupts(oldirqstate);
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}
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void
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ifpga_intr_dispatch(struct clockframe *frame)
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{
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struct intrq *iq;
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struct intrhand *ih;
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int oldirqstate, pcpl, irq, ibit, hwpend;
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pcpl = current_spl_level;
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hwpend = ifpga_iintsrc_read();
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/*
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* Disable all the interrupts that are pending. We will
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* reenable them once they are processed and not masked.
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*/
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intr_enabled &= ~hwpend;
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ifpga_set_intrmask();
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/* Wait for these interrupts to be suppressed. */
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while ((ifpga_iintsrc_read() & hwpend) != 0)
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;
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while (hwpend != 0) {
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irq = ffs(hwpend) - 1;
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ibit = (1U << irq);
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hwpend &= ~ibit;
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if (pcpl & ibit) {
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/*
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* IRQ is masked; mark it as pending and check
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* the next one. Note: the IRQ is already disabled.
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*/
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ifpga_ipending |= ibit;
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continue;
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}
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ifpga_ipending &= ~ibit;
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iq = &intrq[irq];
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iq->iq_ev.ev_count++;
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uvmexp.intrs++;
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current_spl_level |= iq->iq_mask;
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oldirqstate = enable_interrupts(I32_bit);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list)) {
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(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
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}
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restore_interrupts(oldirqstate);
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current_spl_level = pcpl;
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hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl;
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/* Re-enable this interrupt now that's it's cleared. */
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intr_enabled |= ibit;
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ifpga_set_intrmask();
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}
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/* Check for pendings soft intrs. */
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if ((ifpga_ipending & INT_SWMASK) & ~current_spl_level) {
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oldirqstate = enable_interrupts(I32_bit);
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ifpga_do_pending();
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restore_interrupts(oldirqstate);
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}
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}
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