65 lines
2.5 KiB
C
65 lines
2.5 KiB
C
/* $NetBSD: spdreg.h,v 1.4 2014/03/31 11:25:49 martin Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* spd (PlayStation 2 HDD UNIT) common register define.
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*/
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/* interrupt */
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#define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a)
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#define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028)
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#define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128)
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#define SPD_INTR_EMAC3 0x0040
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#define SPD_INTR_RXEND 0x0020
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#define SPD_INTR_TXEND 0x0010
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#define SPD_INTR_RXDNV 0x0008
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#define SPD_INTR_TXDNV 0x0004
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#define SPD_INTR_HDD 0x0001
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/* I/O port */
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#define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c)
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#define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e)
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/* HDD LED */
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#define SPD_IO_LED 0x0001
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/* EEPROM (ethernet address) */
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#define SPD_IO_OUT 0x0010
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#define SPD_IO_IN 0x0020
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#define SPD_IO_CLK 0x0040
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#define SPD_IO_CS 0x0080
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/* HDD interface */
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#define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032)
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#define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040)
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#define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064)
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#define SPD_IF_CTRL_ATA_RST 0x80
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#define SPD_IF_CTRL_DMA_EN 0x04
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