758 lines
21 KiB
C
758 lines
21 KiB
C
/* $NetBSD: s3c2800_pci.c,v 1.7 2003/07/15 00:24:49 lukem Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* derived from evbarm/ifpga/ifpga_pci.c
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*/
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (c) 1997,1998 Mark Brinicombe.
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* Copyright (c) 1997,1998 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* PCI configuration support for Samsung s3c2800.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2800_pci.c,v 1.7 2003/07/15 00:24:49 lukem Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <arm/s3c2xx0/s3c2800reg.h>
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#include <arm/s3c2xx0/s3c2800var.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pciconf.h>
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#include "opt_pci.h"
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#include "pci.h"
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/*
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* pci tag encoding.
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* also useful for configuration type 0 address
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*/
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#define BUSNO_SHIFT 16
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#define BUSNO_MASK (0xff<<BUSNO_SHIFT)
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#define DEVNO_SHIFT 11
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#define DEVNO_MASK (0x1f<<DEVNO_SHIFT)
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#define tag_to_devno(tag) (((tag)&DEVNO_MASK)>>DEVNO_SHIFT)
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#define FUNNO_SHIFT 8
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#define FUNNO_MASK (0x07<<FUNNO_SHIFT)
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#define BUS0_DEV_MIN 1
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#define BUS0_DEV_MAX 21
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void s3c2800_pci_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int s3c2800_pci_bus_maxdevs(void *, int);
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pcitag_t s3c2800_pci_make_tag(void *, int, int, int);
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void s3c2800_pci_decompose_tag(void *, pcitag_t, int *, int *, int *);
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pcireg_t s3c2800_pci_conf_read(void *, pcitag_t, int);
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void s3c2800_pci_conf_write(void *, pcitag_t, int, pcireg_t);
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int s3c2800_pci_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
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const char *s3c2800_pci_intr_string(void *, pci_intr_handle_t);
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const struct evcnt *s3c2800_pci_intr_evcnt(void *, pci_intr_handle_t);
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void * s3c2800_pci_intr_establish(void *, pci_intr_handle_t, int,
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int (*) (void *), void *);
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void s3c2800_pci_intr_disestablish(void *, void *);
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#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
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#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
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struct sspci_irq_handler {
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int (*func) (void *);
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void *arg;
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int level;
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SLIST_ENTRY(sspci_irq_handler) link;
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};
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struct sspci_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_reg_ioh;
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bus_space_handle_t sc_conf0_ioh; /* config type0 space */
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bus_space_handle_t sc_conf1_ioh; /* config type1 space */
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uint32_t sc_pciinten; /* copy of PCIINTEN register */
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/* list of interrupt handlers. SLIST is not good for removing
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* element from it, but intr_disestablish is rarely called */
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SLIST_HEAD(, sspci_irq_handler) sc_irq_handlers;
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void *sc_softinterrupt;
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};
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static int sspci_match(struct device *, struct cfdata *, void *aux);
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static void sspci_attach(struct device *, struct device *, void *);
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static int sspci_bs_map(void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *);
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static int sspci_init_controller(struct sspci_softc *);
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static int sspci_intr(void *);
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static void sspci_softintr(void *);
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/* attach structures */
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CFATTACH_DECL(sspci, sizeof(struct sspci_softc), sspci_match, sspci_attach,
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NULL, NULL);
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struct arm32_pci_chipset sspci_chipset = {
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NULL, /* conf_v */
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s3c2800_pci_attach_hook,
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s3c2800_pci_bus_maxdevs,
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s3c2800_pci_make_tag,
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s3c2800_pci_decompose_tag,
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s3c2800_pci_conf_read,
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s3c2800_pci_conf_write,
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NULL, /* intr_v */
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s3c2800_pci_intr_map,
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s3c2800_pci_intr_string,
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s3c2800_pci_intr_evcnt,
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s3c2800_pci_intr_establish,
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s3c2800_pci_intr_disestablish
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};
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/*
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* bus space tag for PCI IO/Memory access space.
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* filled in by sspci_attach()
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*/
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struct bus_space sspci_io_tag, sspci_mem_tag;
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static int
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sspci_match(struct device *parent, struct cfdata *match, void *aux)
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{
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return 1;
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}
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static int
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sspci_print(void *aux, const char *pnp)
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{
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struct pcibus_attach_args *pci_pba = (struct pcibus_attach_args *) aux;
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if (pnp)
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aprint_normal("%s at %s", pci_pba->pba_busname, pnp);
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if (strcmp(pci_pba->pba_busname, "pci") == 0)
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aprint_normal(" bus %d", pci_pba->pba_bus);
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return UNCONF;
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}
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static void
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sspci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct sspci_softc *sc = (struct sspci_softc *) self;
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struct s3c2xx0_attach_args *aa = aux;
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bus_space_tag_t iot;
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bus_dma_tag_t pci_dma_tag;
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const char *error_on; /* for panic message */
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#if defined(PCI_NETBSD_CONFIGURE)
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struct extent *ioext, *memext;
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struct pcibus_attach_args pci_pba;
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#endif
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#define FAIL(which) do { \
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error_on=(which); goto abort; }while(/*CONSTCOND*/0)
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iot = sc->sc_iot = aa->sa_iot;
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if (bus_space_map(iot, S3C2800_PCICTL_BASE,
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S3C2800_PCICTL_SIZE, 0, &sc->sc_reg_ioh))
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FAIL("control regs");
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if (bus_space_map(iot, S3C2800_PCI_CONF0_BASE,
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S3C2800_PCI_CONF0_SIZE, 0, &sc->sc_conf0_ioh))
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FAIL("config type 0 area");
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#if 0
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if (bus_space_map(iot, S3C2800_PCI_CONF1_BASE,
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S3C2800_PCI_CONF1_SIZE, 0, &sc->sc_conf1_ioh))
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FAIL("config type 1 area");
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#endif
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printf("\n");
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SLIST_INIT(&sc->sc_irq_handlers);
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if (!s3c2800_intr_establish(S3C2800_INT_PCI, IPL_AUDIO, IST_LEVEL,
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sspci_intr, sc))
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FAIL("intr_establish");
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sc->sc_softinterrupt = softintr_establish(IPL_SOFT,
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sspci_softintr, sc);
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if (sc->sc_softinterrupt == NULL)
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FAIL("softintr_establish");
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#if defined(PCI_NETBSD_CONFIGURE)
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if (sspci_init_controller(sc)) {
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printf("%s: failed to initialize controller\n", self->dv_xname);
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return;
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}
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#endif
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sc->sc_pciinten =
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PCIINT_INA | PCIINT_SER | PCIINT_TPE | PCIINT_MPE |
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PCIINT_MFE | PCIINT_PRA | PCIINT_PRD;
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bus_space_write_4(iot, sc->sc_reg_ioh, PCICTL_PCIINTEN,
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sc->sc_pciinten);
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{
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pcireg_t id_reg, class_reg;
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char buf[1000];
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id_reg = bus_space_read_4(iot, sc->sc_reg_ioh,
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PCI_ID_REG);
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class_reg = bus_space_read_4(iot,
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sc->sc_reg_ioh, PCI_CLASS_REG);
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pci_devinfo(id_reg, class_reg, 1, buf);
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printf("%s: %s\n", self->dv_xname, buf);
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}
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#if defined(PCI_NETBSD_CONFIGURE)
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ioext = extent_create("pciio", 0x100, S3C2800_PCI_IOSPACE_SIZE - 0x100,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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memext = extent_create("pcimem", 0, S3C2800_PCI_MEMSPACE_SIZE,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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sspci_chipset.pc_conf_v = (void *) sc;
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sspci_chipset.pc_intr_v = (void *) sc;
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pci_configure_bus(&sspci_chipset, ioext, memext, NULL, 0,
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arm_dcache_align);
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extent_destroy(memext);
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extent_destroy(ioext);
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#endif /* PCI_NETBSD_CONFIGURE */
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/* initialize bus space tag */
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sspci_io_tag = *iot;
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sspci_io_tag.bs_cookie = (void *) S3C2800_PCI_IOSPACE_BASE;
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sspci_io_tag.bs_map = sspci_bs_map;
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sspci_mem_tag = *iot;
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sspci_mem_tag.bs_cookie = (void *) S3C2800_PCI_MEMSPACE_BASE;
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sspci_mem_tag.bs_map = sspci_bs_map;
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/* Platform provides PCI DMA tag */
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pci_dma_tag = s3c2800_pci_dma_init();
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pci_pba.pba_busname = "pci";
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pci_pba.pba_pc = &sspci_chipset;
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pci_pba.pba_iot = &sspci_io_tag;
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pci_pba.pba_memt = &sspci_mem_tag;
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pci_pba.pba_dmat = pci_dma_tag;
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pci_pba.pba_dmat64 = NULL;
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pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pci_pba.pba_bus = 0;
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pci_pba.pba_bridgetag = NULL;
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config_found(self, &pci_pba, sspci_print);
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return;
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#undef FAIL
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abort:
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panic("%s: map failed (%s)",
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self->dv_xname, error_on);
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}
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static int
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sspci_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
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bus_space_handle_t * bshp)
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{
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bus_addr_t startpa, endpa;
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vaddr_t va;
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#ifdef PCI_DEBUG
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printf("sspci_bs_map: t=%p, addr=%lx, size=%lx, flag=%d\n",
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t, bpa, size, flag);
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#endif
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/* Round the allocation to page boundries */
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startpa = trunc_page(bpa);
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endpa = round_page(bpa + size);
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/* Get some VM. */
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va = uvm_km_valloc(kernel_map, endpa - startpa);
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if (va == 0)
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return ENOMEM;
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/* Store the bus space handle */
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*bshp = va + (bpa & PGOFSET);
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/* Now map the pages */
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/* The cookie is the physical base address for PCI I/O or memory area */
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while (startpa < endpa) {
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/* XXX pmap_kenter_pa maps pages cacheable -- not what we
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* want. */
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pmap_enter(pmap_kernel(), va, (bus_addr_t) t + startpa,
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VM_PROT_READ | VM_PROT_WRITE, 0);
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va += PAGE_SIZE;
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startpa += PAGE_SIZE;
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}
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pmap_update(pmap_kernel());
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return 0;
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int func,
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int swiz, int *iline)
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{
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#ifdef PCI_DEBUG
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printf("pci_conf_interrupt(pc(%lx), bus(%d), dev(%d), func(%d), swiz(%d), *iline(%p)\n", (unsigned long) pc, bus, dev, func, swiz, iline);
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#endif
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if (bus == 0) {
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*iline = dev;
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} else {
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panic("pci_conf_interrupt: bus=%d: not yet implemented", bus);
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}
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}
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void
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s3c2800_pci_attach_hook(struct device * parent, struct device * self,
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struct pcibus_attach_args * pba)
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{
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/* Nothing to do. */
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#ifdef PCI_DEBUG
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printf("s3c2800_pci_attach_hook()\n");
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#endif
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}
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int
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s3c2800_pci_bus_maxdevs(void *v, int busno)
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{
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#ifdef PCI_DEBUG
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printf("s3c2800_pci_bus_maxdevs(v=%p, busno=%d)\n", v, busno);
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#endif
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return (32);
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}
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pcitag_t
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s3c2800_pci_make_tag(void *v, int bus, int device, int function)
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{
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return ((bus << BUSNO_SHIFT) | (device << DEVNO_SHIFT) |
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(function << FUNNO_SHIFT));
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}
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void
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s3c2800_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> BUSNO_SHIFT) & 0xff;
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if (dp != NULL)
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*dp = (tag >> DEVNO_SHIFT) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> FUNNO_SHIFT) & 0x7;
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}
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static vaddr_t
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make_pci_conf_va(struct sspci_softc * sc, pcitag_t tag, int offset)
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{
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if ((tag & BUSNO_MASK) == 0) {
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/* configuration type 0 */
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int devno = tag_to_devno(tag);
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if (devno < BUS0_DEV_MIN || BUS0_DEV_MAX < devno)
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return 0;
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return (vaddr_t) bus_space_vaddr(sc->sc_iot, sc->sc_conf0_ioh) +
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(tag & (DEVNO_MASK | FUNNO_MASK)) + offset;
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} else {
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/* XXX */
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return (vaddr_t) - 1; /* cause fault */
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}
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}
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pcireg_t
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s3c2800_pci_conf_read(void *v, pcitag_t tag, int offset)
|
|
{
|
|
struct sspci_softc *sc = v;
|
|
vaddr_t va = make_pci_conf_va(sc, tag, offset);
|
|
int s;
|
|
pcireg_t rv;
|
|
|
|
#ifdef PCI_DEBUG
|
|
printf("s3c2800_pci_conf_read: base=%lx tag=%lx offset=%x\n",
|
|
sc->sc_conf0_ioh, tag, offset);
|
|
#endif
|
|
if (va == 0)
|
|
return -1;
|
|
|
|
PCI_CONF_LOCK(s);
|
|
|
|
if (badaddr_read((void *) va, sizeof(rv), &rv)) {
|
|
#if PCI_DEBUG
|
|
printf("conf_read: %lx bad address\n", va);
|
|
#endif
|
|
rv = (pcireg_t) - 1;
|
|
}
|
|
PCI_CONF_UNLOCK(s);
|
|
|
|
return rv;
|
|
}
|
|
|
|
void
|
|
s3c2800_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
|
|
{
|
|
struct sspci_softc *sc = v;
|
|
vaddr_t va = make_pci_conf_va(sc, tag, offset);
|
|
u_int s;
|
|
|
|
#ifdef PCI_DEBUG
|
|
printf("s3c2800_pci_conf_write: tag=%lx offset=%x -> va=%lx\n", tag, offset, va);
|
|
#endif
|
|
|
|
PCI_CONF_LOCK(s);
|
|
|
|
*(pcireg_t *) va = val;
|
|
|
|
PCI_CONF_UNLOCK(s);
|
|
}
|
|
|
|
void *
|
|
s3c2800_pci_intr_establish(void *pcv, pci_intr_handle_t ih, int level,
|
|
int (*func) (void *), void *arg)
|
|
{
|
|
struct sspci_softc *sc = pcv;
|
|
struct sspci_irq_handler *handler;
|
|
int s;
|
|
|
|
#ifdef PCI_DEBUG
|
|
printf("s3c2800_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, "
|
|
"func=%p, arg=%p)\n", pcv, ih, level, func, arg);
|
|
#endif
|
|
|
|
handler = malloc(sizeof *handler, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
|
|
if (handler == NULL)
|
|
panic("sspci_intr_establish: can't malloc handler info");
|
|
|
|
handler->func = func;
|
|
handler->arg = arg;
|
|
handler->level = level;
|
|
|
|
s = splhigh();
|
|
SLIST_INSERT_HEAD(&sc->sc_irq_handlers, handler, link);
|
|
splx(s);
|
|
|
|
return (handler);
|
|
}
|
|
|
|
void
|
|
s3c2800_pci_intr_disestablish(void *pcv, void *cookie)
|
|
{
|
|
struct sspci_softc *sc = pcv;
|
|
struct sspci_irq_handler *ih = cookie;
|
|
int s;
|
|
|
|
#ifdef PCI_DEBUG
|
|
printf("s3c2800_pci_intr_disestablish(pcv=%p, cookie=%p)\n",
|
|
pcv, cookie);
|
|
#endif
|
|
|
|
s = splhigh();
|
|
SLIST_REMOVE(&sc->sc_irq_handlers, ih, sspci_irq_handler, link);
|
|
splx(s);
|
|
}
|
|
|
|
int
|
|
s3c2800_pci_intr_map(struct pci_attach_args * pa, pci_intr_handle_t * ihp)
|
|
{
|
|
#ifdef PCI_DEBUG
|
|
int pin = pa->pa_intrpin;
|
|
void *pcv = pa->pa_pc;
|
|
pcitag_t intrtag = pa->pa_intrtag;
|
|
int bus, device, function;
|
|
|
|
s3c2800_pci_decompose_tag(pcv, intrtag, &bus, &device, &function);
|
|
printf("s3c2800_pci_intr_map: pcv=%p, tag=%08lx pin=%d dev=%d\n",
|
|
pcv, intrtag, pin, device);
|
|
#endif
|
|
|
|
|
|
/* S3C2800 has only one interrupt line for PCI */
|
|
*ihp = 0;
|
|
return 0;
|
|
}
|
|
|
|
const char *
|
|
s3c2800_pci_intr_string(void *pcv, pci_intr_handle_t ih)
|
|
{
|
|
/* We have only one interrupt source from PCI */
|
|
return "pciint";
|
|
}
|
|
|
|
const struct evcnt *
|
|
s3c2800_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih)
|
|
{
|
|
|
|
/* XXX for now, no evcnt parent reported */
|
|
return NULL;
|
|
}
|
|
/*
|
|
* Initialize PCI controller
|
|
*/
|
|
int
|
|
sspci_init_controller(struct sspci_softc * sc)
|
|
{
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_reg_ioh;
|
|
|
|
/* disable PCI command */
|
|
bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG,
|
|
0xffff0000);
|
|
|
|
/* latency=0x10, cacheline=8 */
|
|
bus_space_write_4(iot, ioh, PCI_BHLC_REG,
|
|
PCI_BHLC_CODE(0, 0, 0, 0x10, 8));
|
|
|
|
bus_space_write_4(iot, ioh, PCI_INTERRUPT_REG,
|
|
PCI_INTERRUPT_CODE(0, 0, 0, 0));
|
|
|
|
|
|
|
|
#if 1
|
|
bus_space_write_4(iot, ioh, PCI_MAPREG_START,
|
|
PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000);
|
|
/* Cover all DBANKs with BAR0 */
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xf8000000);
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, S3C2800_DBANK0_START);
|
|
#else
|
|
bus_space_write_4(iot, ioh, PCI_MAPREG_START,
|
|
PCI_MAPREG_MEM_TYPE_32BIT | 0xf0000000);
|
|
bus_space_write_4(iot, ioh, PCI_MAPREG_START + 4,
|
|
PCI_MAPREG_MEM_TYPE_32BIT | 0x80000000);
|
|
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBAM0, 0xffff0000);
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBATPA0, 0xffff0000);
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBAM1, 0xf1000000);
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIBATPA1, S3C2800_DBANK0_START);
|
|
#endif
|
|
|
|
bus_space_write_4(iot, ioh, PCI_COMMAND_STATUS_REG,
|
|
PCI_STATUS_PARITY_DETECT |
|
|
PCI_STATUS_SPECIAL_ERROR |
|
|
PCI_STATUS_MASTER_ABORT |
|
|
PCI_STATUS_MASTER_TARGET_ABORT |
|
|
PCI_STATUS_TARGET_TARGET_ABORT |
|
|
PCI_STATUS_DEVSEL_MEDIUM |
|
|
PCI_STATUS_PARITY_ERROR |
|
|
PCI_STATUS_BACKTOBACK_SUPPORT |
|
|
PCI_STATUS_CAPLIST_SUPPORT |
|
|
PCI_COMMAND_MASTER_ENABLE |
|
|
PCI_COMMAND_MEM_ENABLE |
|
|
PCI_COMMAND_IO_ENABLE);
|
|
|
|
bus_space_write_4(iot, ioh, PCICTL_PCICON,
|
|
PCICON_ARB | PCICON_HST);
|
|
|
|
bus_space_write_4(iot, ioh, PCICTL_PCISET, 0);
|
|
/* clear all interrupts */
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIINTST, 0xffffffff);
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIINTEN, 0);
|
|
|
|
bus_space_write_4(iot, ioh, PCICTL_PCICON,
|
|
PCICON_RDY | PCICON_CFD | PCICON_ATS |
|
|
PCICON_ARB | PCICON_HST);
|
|
|
|
|
|
#ifdef PCI_DEBUG
|
|
{
|
|
pcireg_t reg;
|
|
int i;
|
|
|
|
for (i = 0; i <= 0x40; i += sizeof(pcireg_t)) {
|
|
reg = bus_space_read_4(iot, ioh, i);
|
|
printf("%03x: %08x\n", i, reg);
|
|
}
|
|
for (i = 0x100; i <= 0x154; i += sizeof(pcireg_t)) {
|
|
reg = bus_space_read_4(iot, ioh, i);
|
|
printf("%03x: %08x\n", i, reg);
|
|
}
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
|
|
static const char *pci_abnormal_error_name[] = {
|
|
"PCI reset deasserted",
|
|
"PCI reset asserted",
|
|
"PCI master detected fatal error",
|
|
"PCI master detected parity error",
|
|
"PCI target detected parity error",
|
|
"PCI SERR# asserted",
|
|
};
|
|
|
|
static int
|
|
sspci_intr(void *arg)
|
|
{
|
|
struct sspci_softc *sc = arg;
|
|
int s;
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_reg_ioh;
|
|
uint32_t interrupts, errors;
|
|
|
|
interrupts = bus_space_read_4(iot, ioh, PCICTL_PCIINTST);
|
|
|
|
if (interrupts & PCIINT_INA) {
|
|
s = splhigh();
|
|
softintr_schedule(sc->sc_softinterrupt);
|
|
|
|
/* mask INTA itnerrupt until softinterrupt is handled */
|
|
sc->sc_pciinten &= ~PCIINT_INA;
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIINTEN,
|
|
sc->sc_pciinten);
|
|
|
|
/* acknowledge INTA interrupt */
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIINTST, PCIINT_INA);
|
|
|
|
splx(s);
|
|
|
|
interrupts &= ~PCIINT_INA;
|
|
|
|
}
|
|
errors = interrupts & (PCIINT_SER | PCIINT_TPE | PCIINT_MPE |
|
|
PCIINT_MFE | PCIINT_PRA | PCIINT_PRD);
|
|
if (errors) {
|
|
int i;
|
|
|
|
for (i = 0; errors; ++i) {
|
|
if ((errors & (1 << i)) == 0)
|
|
continue;
|
|
|
|
printf("%s: %s\n", sc->sc_dev.dv_xname,
|
|
pci_abnormal_error_name[i > 4 ? 5 : i]);
|
|
|
|
errors &= ~(1 << i);
|
|
}
|
|
/* acknowledge interrupts */
|
|
bus_space_write_4(iot, ioh, PCICTL_PCIINTST, interrupts);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
sspci_softintr(void *arg)
|
|
{
|
|
struct sspci_softc *sc = arg;
|
|
struct sspci_irq_handler *ih;
|
|
int s;
|
|
|
|
|
|
SLIST_FOREACH(ih, &(sc->sc_irq_handlers), link) {
|
|
s = _splraise(ih->level);
|
|
ih->func(ih->arg);
|
|
splx(s);
|
|
}
|
|
|
|
/* unmask INTA interrupt */
|
|
s = splhigh();
|
|
sc->sc_pciinten |= PCIINT_INA;
|
|
bus_space_write_4(sc->sc_iot, sc->sc_reg_ioh, PCICTL_PCIINTEN,
|
|
sc->sc_pciinten);
|
|
splx(s);
|
|
}
|