319 lines
9.5 KiB
C
319 lines
9.5 KiB
C
/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Fleischer <paul@xpg.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Derived from s3c2410.c */
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/*
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* Copyright (c) 2003, 2005 Genetec corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2440.c,v 1.2 2012/10/27 17:17:40 chs Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <sys/bus.h>
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#include <arm/cpufunc.h>
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#include <arm/mainbus/mainbus.h>
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#include <arm/s3c2xx0/s3c2440reg.h>
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#include <arm/s3c2xx0/s3c2440var.h>
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#include <arm/s3c2xx0/s3c2440_dma.h>
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#include "locators.h"
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#include "opt_cpuoptions.h"
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/* prototypes */
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static int s3c2440_match(device_t, cfdata_t, void *);
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static void s3c2440_attach(device_t, device_t, void *);
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static int s3c2440_search(device_t, cfdata_t, const int *, void *);
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/* attach structures */
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CFATTACH_DECL_NEW(ssio, sizeof(struct s3c24x0_softc), s3c2440_match, s3c2440_attach,
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NULL, NULL);
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extern struct bus_space s3c2xx0_bs_tag;
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struct s3c2xx0_softc *s3c2xx0_softc;
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#ifdef DEBUG_PORTF
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volatile uint8_t *portf; /* for debug */
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#endif
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static int
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s3c2440_print(void *aux, const char *name)
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{
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struct s3c2xx0_attach_args *sa = (struct s3c2xx0_attach_args *) aux;
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if (sa->sa_size)
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aprint_normal(" addr 0x%lx", sa->sa_addr);
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if (sa->sa_size > 1)
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aprint_normal("-0x%lx", sa->sa_addr + sa->sa_size - 1);
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if (sa->sa_intr != SSIOCF_INTR_DEFAULT)
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aprint_normal(" intr %d", sa->sa_intr);
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if (sa->sa_index != SSIOCF_INDEX_DEFAULT)
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aprint_normal(" unit %d", sa->sa_index);
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return (UNCONF);
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}
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int
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s3c2440_match(device_t parent, cfdata_t match, void *aux)
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{
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return 1;
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}
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void
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s3c2440_attach(device_t parent, device_t self, void *aux)
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{
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struct s3c24x0_softc *sc = device_private(self);
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bus_space_tag_t iot;
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const char *which_registers; /* for panic message */
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#define FAIL(which) do { \
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which_registers=(which); goto abort; }while(/*CONSTCOND*/0)
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s3c2xx0_softc = &(sc->sc_sx);
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sc->sc_sx.sc_iot = iot = &s3c2xx0_bs_tag;
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if (bus_space_map(iot,
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S3C2440_INTCTL_BASE, S3C2440_INTCTL_SIZE,
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BUS_SPACE_MAP_LINEAR, &sc->sc_sx.sc_intctl_ioh))
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FAIL("intc");
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/* tell register addresses to interrupt handler */
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s3c2440_intr_init(sc);
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/* Map the GPIO registers */
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if (bus_space_map(iot, S3C2440_GPIO_BASE, S3C2440_GPIO_SIZE,
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0, &sc->sc_sx.sc_gpio_ioh))
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FAIL("GPIO");
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#ifdef DEBUG_PORTF
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{
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extern volatile uint8_t *portf;
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/* make all ports output */
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bus_space_write_2(iot, sc->sc_sx.sc_gpio_ioh, GPIO_PCONF, 0x5555);
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portf = (volatile uint8_t *)
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((char *)bus_space_vaddr(iot, sc->sc_sx.sc_gpio_ioh) + GPIO_PDATF);
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}
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#endif
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#if 1
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/* Map the DMA controller registers */
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if (bus_space_map(iot, S3C2440_DMAC_BASE, S3C2440_DMAC_SIZE,
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0, &sc->sc_sx.sc_dmach))
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FAIL("DMAC");
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#endif
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/* Memory controller */
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if (bus_space_map(iot, S3C2440_MEMCTL_BASE,
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S3C24X0_MEMCTL_SIZE, 0, &sc->sc_sx.sc_memctl_ioh))
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FAIL("MEMC");
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/* Clock manager */
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if (bus_space_map(iot, S3C2440_CLKMAN_BASE,
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S3C24X0_CLKMAN_SIZE, 0, &sc->sc_sx.sc_clkman_ioh))
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FAIL("CLK");
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#if 0
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/* Real time clock */
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if (bus_space_map(iot, S3C2410_RTC_BASE,
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S3C24X0_RTC_SIZE, 0, &sc->sc_sx.sc_rtc_ioh))
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FAIL("RTC");
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#endif
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if (bus_space_map(iot, S3C2440_TIMER_BASE,
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S3C24X0_TIMER_SIZE, 0, &sc->sc_timer_ioh)) {
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FAIL("TIMER");
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}
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/* calculate current clock frequency */
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s3c24x0_clock_freq(&sc->sc_sx);
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aprint_normal(": fclk %d MHz hclk %d MHz pclk %d MHz\n",
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sc->sc_sx.sc_fclk / 1000000, sc->sc_sx.sc_hclk / 1000000,
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sc->sc_sx.sc_pclk / 1000000);
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aprint_naive("\n");
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/* get busdma tag for the platform */
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sc->sc_sx.sc_dmat = s3c2xx0_bus_dma_init(&s3c2xx0_bus_dma);
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s3c2440_dma_init();
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/*
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* Attach devices.
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*/
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config_search_ia(s3c2440_search, self, "ssio", NULL);
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return;
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abort:
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panic("%s: unable to map %s registers",
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device_xname(self), which_registers);
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#undef FAIL
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}
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int
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s3c2440_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
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{
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struct s3c24x0_softc *sc = device_private(parent);
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struct s3c2xx0_attach_args aa;
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aa.sa_sc = sc;
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aa.sa_iot = sc->sc_sx.sc_iot;
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aa.sa_addr = cf->cf_loc[SSIOCF_ADDR];
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aa.sa_size = cf->cf_loc[SSIOCF_SIZE];
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aa.sa_index = cf->cf_loc[SSIOCF_INDEX];
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aa.sa_intr = cf->cf_loc[SSIOCF_INTR];
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aa.sa_dmat = sc->sc_sx.sc_dmat;
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if (config_match(parent, cf, &aa))
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config_attach(parent, cf, &aa, s3c2440_print);
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return 0;
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}
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/*
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* fill sc_pclk, sc_hclk, sc_fclk from values of clock controller register.
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*
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* s3c24x0_clock_freq2() is meant to be called from kernel startup routines.
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* s3c24x0_clock_freq() is for after kernel initialization is done.
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*/
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void
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s3c24x0_clock_freq2(vaddr_t clkman_base, int *fclk, int *hclk, int *pclk)
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{
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uint32_t pllcon, divn, camdivn;
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int mdiv, pdiv, sdiv;
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uint32_t f, h, p;
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pllcon = *(volatile uint32_t *)(clkman_base + CLKMAN_MPLLCON);
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divn = *(volatile uint32_t *)(clkman_base + CLKMAN_CLKDIVN);
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camdivn = *(volatile uint32_t *)(clkman_base + CLKMAN_CAMDIVN);
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mdiv = (pllcon & PLLCON_MDIV_MASK) >> PLLCON_MDIV_SHIFT;
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pdiv = (pllcon & PLLCON_PDIV_MASK) >> PLLCON_PDIV_SHIFT;
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sdiv = (pllcon & PLLCON_SDIV_MASK) >> PLLCON_SDIV_SHIFT;
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f = ((mdiv + 8) * S3C2XX0_XTAL_CLK) / ((pdiv + 2) * (1 << sdiv)) * 2;
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h = f;
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/* HDIVN of CLKDIVN can have 4 distinct values */
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switch( (divn & CLKDIVN_HDIVN_MASK) >> CLKDIVN_HDIVN_SHIFT )
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{
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case 0:
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/* 00b: HCLK = FCLK/1*/
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break;
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case 1:
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/* 01b: HCLK = FCLK/2*/
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h /= 2;
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break;
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case 2:
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/* 10b: HCLK = FCLK/4 when CAMDIVN[9] (HCLK4_HALF) = 0
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* HCLK = FCLK/8 when CAMDIVN[9] (HCLK4_HALF) = 1 */
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if( camdivn & CLKCAMDIVN_HCLK4_HALF )
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h /= 8;
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else
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h /= 4;
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break;
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case 3:
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/* 11b: HCLK = FCLK/3 when CAMDIVN[8] (HCLK3_HALF) = 0
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* HCLK = FCLK/6 when CAMDIVN[8] (HCLK3_HALF) = 1 */
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if( camdivn & CLKCAMDIVN_HCLK3_HALF )
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h /= 6;
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else
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h /= 3;
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break;
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}
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p = h;
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if (divn & CLKDIVN_PDIVN)
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p /= 2;
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if (fclk) *fclk = f;
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if (hclk) *hclk = h;
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if (pclk) *pclk = p;
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}
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void
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s3c24x0_clock_freq(struct s3c2xx0_softc *sc)
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{
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s3c24x0_clock_freq2(
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(vaddr_t)bus_space_vaddr(sc->sc_iot, sc->sc_clkman_ioh),
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&sc->sc_fclk, &sc->sc_hclk, &sc->sc_pclk);
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}
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/*
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* Issue software reset command.
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* called with MMU off.
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*
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* S3C2410 doesn't have sowtware reset bit like S3C2800.
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* use watch dog timer and make it fire immediately.
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*/
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void
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s3c2440_softreset(void)
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{
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disable_interrupts(I32_bit|F32_bit);
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*(volatile unsigned int *)(S3C2440_WDT_BASE + WDT_WTCON)
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= (0 << WTCON_PRESCALE_SHIFT) | WTCON_ENABLE |
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WTCON_CLKSEL_16 | WTCON_ENRST;
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}
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