0d7e99a27a
Most of the testing was done on MIPS hardware -- it probably needs work before
it will be useful with x86 hardware, and it is probably incompatible with
the X11 server.
"ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
does not endorse, this software. ATI will not be responsible or liable
for any actual or alleged damage or loss caused by or in connection with
the use of or reliance on this software."
Enjoy!
235 lines
6.6 KiB
C
235 lines
6.6 KiB
C
/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* ATI Technologies Inc. ("ATI") has not assisted in the creation of, and
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* does not endorse, this software. ATI will not be responsible or liable
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* for any actual or alleged damage or loss caused by or in connection with
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* the use of or reliance on this software.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: radeonfb_i2c.c,v 1.1 2006/08/16 22:46:45 gdamore Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/i2c_bitbang.h>
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#include <dev/i2c/ddcvar.h>
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#include <dev/pci/radeonfbreg.h>
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#include <dev/pci/radeonfbvar.h>
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/* i2c support */
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static int radeonfb_i2c_acquire_bus(void *, int);
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static void radeonfb_i2c_release_bus(void *, int);
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static int radeonfb_i2c_send_start(void *, int);
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static int radeonfb_i2c_send_stop(void *, int);
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static int radeonfb_i2c_initiate_xfer(void *, i2c_addr_t, int);
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static int radeonfb_i2c_read_byte(void *, uint8_t *, int);
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static int radeonfb_i2c_write_byte(void *, uint8_t, int);
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/* i2c bit-bang glue */
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static void radeonfb_i2cbb_set_bits(void *, uint32_t);
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static void radeonfb_i2cbb_set_dir(void *, uint32_t);
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static uint32_t radeonfb_i2cbb_read(void *);
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/*
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* I2C bit-bang operations
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*/
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void
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radeonfb_i2cbb_set_bits(void *cookie, uint32_t bits)
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{
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struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
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struct radeonfb_softc *sc = ric->ric_softc;
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PATCH32(sc, ric->ric_register, bits,
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~(RADEON_GPIO_A_0 | RADEON_GPIO_A_1));
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}
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void
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radeonfb_i2cbb_set_dir(void *cookie, uint32_t bits)
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{
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struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
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struct radeonfb_softc *sc = ric->ric_softc;
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PATCH32(sc, ric->ric_register, bits, ~(RADEON_GPIO_EN_0));
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}
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uint32_t
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radeonfb_i2cbb_read(void *cookie)
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{
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struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
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struct radeonfb_softc *sc = ric->ric_softc;
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/* output bit is 0 shifted, input bit is shifted 8 */
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return (GET32(sc, ric->ric_register) >> RADEON_GPIO_Y_SHIFT_0);
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}
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static const struct i2c_bitbang_ops radeonfb_i2cbb_ops = {
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radeonfb_i2cbb_set_bits,
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radeonfb_i2cbb_set_dir,
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radeonfb_i2cbb_read,
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{
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RADEON_GPIO_A_0, /* SDA */
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RADEON_GPIO_A_1, /* SCL */
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RADEON_GPIO_EN_0, /* SDA output */
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0, /* SDA input */
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}
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};
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/*
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* I2C support
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*/
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int
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radeonfb_i2c_acquire_bus(void *cookie, int flags)
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{
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struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
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struct radeonfb_softc *sc = ric->ric_softc;
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int i;
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/*
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* Some hardware seems to have hardware/software combined access
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* to the DVI I2C. We want to use software.
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*/
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if (ric->ric_register == RADEON_GPIO_DVI_DDC) {
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/* ask for software access to I2C bus */
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SET32(sc, ric->ric_register, RADEON_GPIO_SW_USE);
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/*
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* wait for the chip to give up access. we don't make
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* this a hard timeout, because some hardware might
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* not implement this negotiation protocol
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*/
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for (i = RADEON_TIMEOUT; i; i--) {
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if (GET32(sc, ric->ric_register) & RADEON_GPIO_SW_USE)
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break;
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}
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}
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/* enable the I2C clock */
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SET32(sc, ric->ric_register, RADEON_GPIO_EN_1);
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return 0;
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}
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void
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radeonfb_i2c_release_bus(void *cookie, int flags)
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{
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struct radeonfb_i2c *ric = (struct radeonfb_i2c *)cookie;
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struct radeonfb_softc *sc = ric->ric_softc;
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if (ric->ric_register == RADEON_GPIO_DVI_DDC) {
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/* we no longer "want" I2C, and we're "done" with it */
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CLR32(sc, ric->ric_register, RADEON_GPIO_SW_USE);
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SET32(sc, ric->ric_register, RADEON_GPIO_SW_DONE);
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}
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}
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int
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radeonfb_i2c_send_start(void *cookie, int flags)
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{
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return i2c_bitbang_send_start(cookie, flags, &radeonfb_i2cbb_ops);
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}
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int
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radeonfb_i2c_send_stop(void *cookie, int flags)
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{
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return i2c_bitbang_send_stop(cookie, flags, &radeonfb_i2cbb_ops);
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}
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int
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radeonfb_i2c_initiate_xfer(void *cookie, i2c_addr_t addr, int flags)
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{
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return i2c_bitbang_initiate_xfer(cookie, addr, flags,
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&radeonfb_i2cbb_ops);
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}
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int
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radeonfb_i2c_read_byte(void *cookie, uint8_t *valp, int flags)
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{
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return i2c_bitbang_read_byte(cookie, valp, flags, &radeonfb_i2cbb_ops);
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}
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int
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radeonfb_i2c_write_byte(void *cookie, uint8_t val, int flags)
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{
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return i2c_bitbang_write_byte(cookie, val, flags, &radeonfb_i2cbb_ops);
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}
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void
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radeonfb_i2c_init(struct radeonfb_softc *sc)
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{
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int i;
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for (i = 0; i < 4; i++) {
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struct i2c_controller *icc = &sc->sc_i2c[i].ric_controller;
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sc->sc_i2c[i].ric_softc = sc;
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icc->ic_cookie = &sc->sc_i2c[i];
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icc->ic_acquire_bus = radeonfb_i2c_acquire_bus;
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icc->ic_release_bus = radeonfb_i2c_release_bus;
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icc->ic_send_start = radeonfb_i2c_send_start;
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icc->ic_send_stop = radeonfb_i2c_send_stop;
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icc->ic_initiate_xfer = radeonfb_i2c_initiate_xfer;
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icc->ic_read_byte = radeonfb_i2c_read_byte;
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icc->ic_write_byte = radeonfb_i2c_write_byte;
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}
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/* index == ddctype (RADEON_DDC_XX) - 1 */
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sc->sc_i2c[0].ric_register = RADEON_GPIO_MONID;
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sc->sc_i2c[1].ric_register = RADEON_GPIO_DVI_DDC;
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sc->sc_i2c[2].ric_register = RADEON_GPIO_VGA_DDC;
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sc->sc_i2c[3].ric_register = RADEON_GPIO_CRT2_DDC;
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}
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int
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radeonfb_i2c_read_edid(struct radeonfb_softc *sc, int ddctype, uint8_t *data)
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{
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if ((ddctype < 1) || (ddctype > 4))
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return EINVAL;
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ddctype--;
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return (ddc_read_edid(&sc->sc_i2c[ddctype].ric_controller, data, 128));
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}
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