131 lines
6.0 KiB
C
131 lines
6.0 KiB
C
/* $NetBSD: sbusreg.h,v 1.4 1998/09/19 15:48:55 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun-4c S-bus definitions. (Should be made generic!)
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*
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* Sbus slot 0 is not a separate slot; it talks to the onboard I/O devices.
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* It is, however, addressed just like any `real' Sbus.
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*
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* Sbus device addresses are obtained from the FORTH PROMs. They come
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* in `absolute' and `relative' address flavors, so we have to handle both.
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* Relative addresses do *not* include the slot number.
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*/
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#define SBUS_BASE 0xf8000000
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#define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off))
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#define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE)
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#define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25)
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#define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff)
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#if _sbus_for_your_eyes_only_
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struct sbusreg {
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u_int32_t sbus_afsr; /* M-to-S Asynchronous Fault Status */
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u_int32_t sbus_afar; /* M-to-S Asynchronous Fault Address */
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u_int32_t sbus_arbiter; /* Arbiter Enable */
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u_int32_t sbus_reserved1;
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#define NSBUSCFG 20
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/* Actual number dependent on machine model */
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u_int32_t sbus_sbuscfg[NSBUSCFG]; /* Sbus configuration control */
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};
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#endif
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/* Register offsets */
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#define SBUS_AFSR_REG 0
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#define SBUS_AFAR_REG 4
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#define SBUS_ARB_REG 8
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#define SBUS_CFG_REG(n) (16 + 4*(n))
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#define SBUS_MFSR_REG 32 /* MS1 only: memory fault status */
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#define SBUS_MFAR_REG 34 /* MS1 only: memory fault address */
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/* M-to-S Asynchronous Fault Status register */
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#define SBUS_AFSR_PAH 0x0000000f /* PA<35:32> of fault address */
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#define SBUS_AFSR_WM 0x00000100 /* SBus wide mode access */
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#define SBUS_AFSR_SSIZ 0x00000e00 /* Size of error transaction */
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#define SBUS_AFSR_SA 0x0001f000 /* bits <4:0> of fault address */
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#define SBUS_AFSR_FAV 0x00020000 /* Fault address valid (MS only) */
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#define SBUS_AFSR_RD 0x00040000 /* Read transaction */
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#define SBUS_AFSR_ME 0x00080000 /* Multiple error */
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#define SBUS_AFSR_MID 0x00f00000 /* Module ID */
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#define SBUS_AFSR_S 0x01000000 /* Supervisor mode */
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#define SBUS_AFSR_SIZ 0x0e000000 /* Requested transaction size */
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#define SBUS_AFSR_BERR 0x10000000 /* Bus error (Sbus) or error ACK (VME)*/
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#define SBUS_AFSR_TO 0x20000000 /* Bus Timeout */
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#define SBUS_AFSR_LE 0x40000000 /* SBus late error */
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#define SBUS_AFSR_ERR 0x80000000 /* Summary bit: one of LE,TO,BERR */
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#define SBUS_AFSR_BITS "\177\020" \
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"f\0\4PAH\0b\10WM\0f\11\3SSIZ\0f\14\5SA\0" \
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"b\11FAV\0b\12RD\0b\13ME\0f\14\4MID\0b\30S\0" \
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"f\31\3SIZ\0b\34BERR\0b\35TO\0b\36LE\0b\37ERR\0"
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/* Arbiter Enable register */
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#define SBUS_ARB_P1 0x00000002 /* Enable MBus master 9 */
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#define SBUS_ARB_P2 0x00000004 /* Enable MBus master 10 */
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#define SBUS_ARB_P3 0x00000008 /* Enable MBus master 11 */
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#define SBUS_ARB_B0 0x00010000 /* Enable SBus Slot 0 */
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#define SBUS_ARB_B1 0x00020000 /* Enable SBus Slot 1 */
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#define SBUS_ARB_B2 0x00040000 /* Enable SBus Slot 2 */
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#define SBUS_ARB_B3 0x00080000 /* Enable SBus Slot 3 */
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#define SBUS_ARB_BF 0x00100000 /* Enable on-board SBus devices */
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#define SBUS_ARB_SBW 0x80000000 /* Enable S-to-M synchronous writes */
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#define SBUS_ARB_BITS "\177\020" \
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"f\0\4CPUs Enabled\0" \
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"f\20\5SBus Slots Enabled\0" \
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"b\37S-to-M synchronous\0"
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/* SBus Slot Configuration register */
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#define SBUS_CFG_BY 0x00000001 /* Bypass Enabled */
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#define SBUS_CFG_BA8 0x00000002 /* Slave supports 8-byte bursts */
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#define SBUS_CFG_BA16 0x00000004 /* Slave supports 16-byte bursts */
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#define SBUS_CFG_BA32 0x00000008 /* Slave supports 32-byte bursts */
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#define SBUS_CFG_BA64 0x00000010 /* Slave supports 64-byte bursts */
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#define SBUS_CFG_WMA 0x00004000 /* Enable wide-mode access */
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#define SBUS_CFG_CP 0x00008000 /* Cacheable bit */
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#define SBUS_CFG_SEGA 0x003f0000 /* PA<35:30> in by-pass mode */
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#define SBUS_CFG_BITS "\177\020" \
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"b\0BY\0b\1BA8\0b\2BA16\0b\3BA32\0b\4BA64\0" \
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"b\16WMA\0b\17CP\0f\20\6SEGA\0"
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