112 lines
4.0 KiB
C
112 lines
4.0 KiB
C
/* $NetBSD: pciide_acer_reg.h,v 1.10 2005/12/11 12:22:50 christos Exp $ */
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/*
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* Copyright (c) 1999 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/* class code attribute register 1 (1 byte) */
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#define ACER_CCAR1 0x43
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#define ACER_CHANSTATUS_RO 0x40
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#define PCIIDE_CHAN_RO(chan) (0x20 >> (chan))
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/* from Linux, 80 pins cable detect */
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#define ACER_0x4A 0x4a
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/*
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* bit 0 is 0 -> primary has 80 pin cable
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* bit 1 is 0 -> secondary has 80 pin cable
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*/
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#define ACER_0x4A_80PIN(chan) (0x1 << (chan))
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/* From FreeBSD, for UDMA mode > 2 */
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#define ACER_0x4B 0x4b
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#define ACER_0x4B_UDMA66 0x01
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/* From Linux */
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#define ACER_0x4B_CDETECT 0x08
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/* class code attribute register 2 (1 byte) */
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#define ACER_CCAR2 0x4d
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#define ACER_CHANSTATUSREGS_RO 0x80
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/* class code attribute register 3 (1 byte) */
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#define ACER_CCAR3 0x50
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#define ACER_CCAR3_PI 0x02
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/* flexible channel setting register */
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#define ACER_FCS 0x52
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#define ACER_FCS_TIMREG(chan,drv) ((0x8) >> ((drv) + (chan) * 2))
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/* CD-ROM control register */
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#define ACER_CDRC 0x53
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#define ACER_CDRC_FIFO_DISABLE 0x02
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#define ACER_CDRC_DMA_EN 0x01
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/* Fifo threshold and Ultra-DMA settings (4 bytes). */
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#define ACER_FTH_UDMA 0x54
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#define ACER_FTH_VAL(chan, drv, val) \
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(((val) & 0x3) << ((drv) * 4 + (chan) * 8))
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#define ACER_FTH_OPL(chan, drv, val) \
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(((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
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#define ACER_UDMA_EN(chan, drv) \
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(0x8 << (16 + (drv) * 4 + (chan) * 8))
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#define ACER_UDMA_TIM(chan, drv, val) \
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(((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
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/* drives timings setup (1 byte) */
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#define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4)
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/* IRQ and drive select status */
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#define ACER_CHIDS 0x75
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#define ACER_CHIDS_DRV(channel) ((0x4) << (channel))
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#define ACER_CHIDS_INT(channel) ((0x1) << (channel))
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/* Linux: south-bridge's enable bit (m1533) */
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#define ACER_0x79 0x79
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#define ACER_0x79_REVC2_EN 0x4
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#define ACER_0x79_EN 0x2
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/* OpenSolaris: channel enable/disable in the PCI-ISA bridge */
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#define ACER_PCIB_CTRL 0x58
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#define ACER_PCIB_CTRL_ENCHAN(chan) (0x4 << (chan))
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/*
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* IDE bus frequency (1 byte)
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* This should be setup by the BIOS - can we rely on this ?
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*/
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#define ACER_IDE_CLK 0x78
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/* acer UDMA3/4/5 from FreeBSD */
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static const int8_t acer_udma[] __attribute__((__unused__)) =
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{0x4, 0x3, 0x2, 0x1, 0x0, 0x7};
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static const int8_t acer_pio[] __attribute__((__unused__)) =
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{0x0c, 0x58, 0x44, 0x33, 0x31};
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#ifdef unused
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static const int8_t acer_dma[] __attribute__((__unused__)) =
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{0x08, 0x33, 0x31};
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#endif
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