78 lines
2.7 KiB
C
78 lines
2.7 KiB
C
/* $NetBSD: dmac3reg.h,v 1.3 2008/04/09 15:43:03 tsutsui Exp $ */
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/*-
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* Copyright (c) 2000 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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struct dmac3reg {
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volatile uint32_t csr;
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volatile uint32_t intr;
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volatile uint32_t len;
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volatile uint32_t addr;
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volatile uint32_t conf;
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};
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#define DMAC3_CSR_DBURST 0x0020
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#define DMAC3_CSR_MBURST 0x0010
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#define DMAC3_CSR_APAD 0x0008
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#define DMAC3_CSR_RESET 0x0004
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#define DMAC3_CSR_RECV 0x0002
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#define DMAC3_CSR_SEND 0x0000
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#define DMAC3_CSR_ENABLE 0x0001
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#define DMAC3_INTR_PERR 0x8000
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#define DMAC3_INTR_DRQI 0x4000
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#define DMAC3_INTR_DRQIE 0x2000
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#define DMAC3_INTR_DREQ 0x1000
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#define DMAC3_INTR_EOPI 0x0400
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#define DMAC3_INTR_EOPIE 0x0200
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#define DMAC3_INTR_EOP 0x0100
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#define DMAC3_INTR_TCI 0x0040
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#define DMAC3_INTR_TCIE 0x0020
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#define DMAC3_INTR_INTEN 0x0002
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#define DMAC3_INTR_INT 0x0001
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#define DMAC3_CONF_IPER 0x8000
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#define DMAC3_CONF_MPER 0x4000
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#define DMAC3_CONF_PCEN 0x2000
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#define DMAC3_CONF_DERR 0x1000
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#define DMAC3_CONF_DCEN 0x0800
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#define DMAC3_CONF_ODDP 0x0200
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#define DMAC3_CONF_WIDTH 0x00ff
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#define DMAC3_CONF_SLOWACCESS 0x0020
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#define DMAC3_CONF_FASTACCESS 0x0001
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#define DMAC3_PAGEMAP 0xb4c20000
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#define DMAC3_MAPSIZE 0x20000
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struct dma_pte {
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uint32_t pad1;
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uint32_t valid:1,
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coherent:1, /* ? */
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pad2:10, /* ? */
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pfnum:20;
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};
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